[PATCH 0/5] ARM: dts: imx6ull-tarragon-common: Fix several issues

[PATCH 0/5] ARM: dts: imx6ull-tarragon-common: Fix several issues

[Stefan Wahren]

This series addresses Ethernet and PMIC related issues on the Tarragon
platform.

Stefan Wahren (5):
  ARM: dts: imx6ull-tarragon-common: Fix Ethernet regression
  ARM: dts: imx6ull-tarragon-common: Fix Ethernet PHY issues
  ARM: dts: imx6ull-tarragon-common: Disable unused LDOs
  ARM: dts: imx6ull-tarragon-common: Fix i.MX6ULL DVFS
  ARM: dts: imx6ull-tarragon-common: Fix vmmc supply

 .../dts/nxp/imx/imx6ull-tarragon-common.dtsi  | 44 +++++++++++--------
 1 file changed, 25 insertions(+), 19 deletions(-)

-- 
2.43.0

[PATCH 1/5] ARM: dts: imx6ull-tarragon-common: Fix Ethernet regression

[Stefan Wahren]

The commit e2ba87c745ca ("ARM: dts: imx6ul: Set macaddress location in ocotp")
introduced a OTP to MAC address mapping on DT level. But the Tarragon
platform relies on a different MAC address mapping, which is provided by
U-Boot. So unfortunately the mentioned commit breaks Ethernet on the
Tarragon platform. Fix this by dropping the additional MAC address mapping.

Fixes: e2ba87c745ca ("ARM: dts: imx6ul: Set macaddress location in ocotp")
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
---
 arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
index 5248a058230c..5622f0ebb7a3 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
@@ -119,6 +119,9 @@ &pinctrl_enet1_phy_rst
 	phy-reset-duration = <25>;
 	phy-handle = <&ethphy0>;
 
+	/delete-property/ nvmem-cells;
+	/delete-property/ nvmem-cell-names;
+
 	mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -139,6 +142,11 @@ ethphy0: ethernet-phy@0 {
 	};
 };
 
+&fec2 {
+	/delete-property/ nvmem-cells;
+	/delete-property/ nvmem-cell-names;
+};
+
 &gpio1 {
 	gpio-line-names = "",				/* 0 */
 			  "",
-- 
2.43.0

[PATCH 2/5] ARM: dts: imx6ull-tarragon-common: Fix Ethernet PHY issues

[Stefan Wahren]

The commit 57ec5a8735dc ("net: phy: smsc: add proper reset flags for LAN8710A")
introduced proper reset handling for the SMSC LAN8710, which is now more
reliable than the PHY handling of the fec driver. So switch to the generic
PHY reset handling on the Tarragon platform.

Fixes: 5e4f393ccbf0 ("ARM: dts: imx6ull: Add chargebyte Tarragon support")
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
---
 arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
index 5622f0ebb7a3..d2aa5285cd18 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
@@ -111,12 +111,9 @@ &ecspi4 {
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet1
-		     &pinctrl_enet1_phy_rst
 		     &pinctrl_enet_mdio>;
 	phy-supply = <&reg_dcdc_3v3>;
 	phy-mode = "rmii";
-	phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
-	phy-reset-duration = <25>;
 	phy-handle = <&ethphy0>;
 
 	/delete-property/ nvmem-cells;
@@ -130,13 +127,16 @@ ethphy0: ethernet-phy@0 {
 			compatible = "ethernet-phy-ieee802.3-c22";
 			reg = <0>;
 			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_enet1_phy_int>;
+			pinctrl-0 = <&pinctrl_enet1_phy_int &pinctrl_enet1_phy_rst>;
 			interrupt-parent = <&gpio2>;
 			interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
 			interrupts-extended = <&gpio2 7 IRQ_TYPE_EDGE_FALLING>;
 			clocks = <&clks IMX6UL_CLK_ENET_REF>;
 			clock-names = "rmii-ref";
 			max-speed = <100>;
+			reset-assert-us = <500>;
+			reset-deassert-us = <500>;
+			reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
 			smsc,disable-energy-detect;
 		};
 	};
-- 
2.43.0

[PATCH 3/5] ARM: dts: imx6ull-tarragon-common: Disable unused LDOs

[Stefan Wahren]

According to the Tarragon schematics LDO2, LDO3 and LDO4 doesn't have any
consumers. So there is no point for regulator-always-on.

Fixes: 5e4f393ccbf0 ("ARM: dts: imx6ull: Add chargebyte Tarragon support")
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
---
 arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
index d2aa5285cd18..81761a505d6f 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
@@ -321,7 +321,6 @@ vgen2_reg: vldo2 {
 				regulator-name = "VLDO2";
 				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <1550000>;
-				regulator-always-on;
 			};
 
 			vgen3_reg: vccsd {
@@ -342,14 +341,12 @@ vgen5_reg: vldo3 {
 				regulator-name = "VLDO3";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
 			};
 
 			vgen6_reg: vldo4 {
 				regulator-name = "VLDO4";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
 			};
 		};
 	};
-- 
2.43.0

[PATCH 4/5] ARM: dts: imx6ull-tarragon-common: Fix i.MX6ULL DVFS

[Stefan Wahren]

During mainlining of the Tarragon boards, we missed to wire up reg_arm
and reg_soc from PMIC to the i.MX6ULL, which result in a constant voltage
during DVFS. While fixing this, give the regulator a better node reference.

Fixes: 5e4f393ccbf0 ("ARM: dts: imx6ull: Add chargebyte Tarragon support")
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
---
 .../boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi    | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
index 81761a505d6f..afbb3be48d71 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
@@ -278,7 +278,7 @@ pfuze3001: pmic@8 {
 		reg = <0x08>;
 
 		regulators {
-			sw1_reg: sw1 {
+			vdd_arm_soc_in: sw1 {
 				regulator-name = "SW1";
 				regulator-min-microvolt = <700000>;
 				regulator-max-microvolt = <3300000>;
@@ -774,6 +774,16 @@ &pwm8 {
 	status = "okay";
 };
 
+&reg_arm {
+	vin-supply = <&vdd_arm_soc_in>;
+	regulator-allow-bypass;
+};
+
+&reg_soc {
+	vin-supply = <&vdd_arm_soc_in>;
+	regulator-allow-bypass;
+};
+
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_rs485_1>;
-- 
2.43.0

[PATCH 5/5] ARM: dts: imx6ull-tarragon-common: Fix vmmc supply

[Stefan Wahren]

reg_dcdc_3v3 and sw2_reg actually represent the same physical regulator,
while the former one is used as vmmc supply for the eMMC. So use the proper
regulator of the PMIC instead, drop the bogus fixed regulator and keep
the better node reference.

Fixes: 5e4f393ccbf0 ("ARM: dts: imx6ull: Add chargebyte Tarragon support")
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
---
 .../boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi   | 13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
index afbb3be48d71..4d1dab19f593 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
@@ -30,15 +30,6 @@ emmc_pwrseq: emmc-pwrseq {
 		reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
 	};
 
-	reg_dcdc_3v3: regulator-dcdc-3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "dcdc-3v3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
 	reg_1v8: regulator-1v8 {
 		compatible = "regulator-fixed";
 		regulator-name = "ldo-1v8";
@@ -286,7 +277,7 @@ vdd_arm_soc_in: sw1 {
 				regulator-always-on;
 			};
 
-			sw2_reg: sw2 {
+			reg_dcdc_3v3: sw2 {
 				regulator-name = "SW2";
 				regulator-min-microvolt = <1500000>;
 				regulator-max-microvolt = <3300000>;
@@ -846,7 +837,7 @@ &usdhc2 {
 	pinctrl-0 = <&pinctrl_usdhc2>;
 	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
-	vmmc-supply = <&sw2_reg>;
+	vmmc-supply = <&reg_dcdc_3v3>;
 	vqmmc-supply = <&reg_1v8>;
 	mmc-pwrseq = <&emmc_pwrseq>;
 	bus-width = <8>;
-- 
2.43.0

Re: [PATCH 2/5] ARM: dts: imx6ull-tarragon-common: Fix Ethernet PHY issues

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] dts: Missing PHY ID in compatible string causes PHY probe failure
- [High] dts: PHY reset pinctrl applied too late due to PHY node placement
- [Medium] dts: PHY reset duration drastically reduced from 25ms to 500us
--

commit f2c57a8f69beb5f6e98a9a695928883c23235853
Author: Stefan Wahren <wahrenst@gmx.net>
ARM: dts: imx6ull-tarragon-common: Fix Ethernet PHY issues

This commit moves the SMSC LAN8710 Ethernet PHY reset handling to the
generic PHY reset properties on the Tarragon platform.

[Severity: High]
In arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi, the ethphy0
node at line 131 sets the compatible string to ethernet-phy-ieee802.3-c22.
Does this missing explicit PHY ID cause the MDIO core to fail device
creation?

When the MDIO bus is registered, fwnode_mdiobus_register_phy in
drivers/net/mdio/fwnode_mdio.c (around line 132) will try to parse the PHY
ID from the compatible string. If it fails, it falls back to
get_phy_device to read the ID directly from the MDIO bus. Since the PHY is
still held in hardware reset during this read, it will receive 0xffff and
return -ENODEV. The generic PHY reset logic runs after the PHY device is
created, creating a chicken-and-egg situation where the PHY is never
detected.

[Severity: High]
In arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi, moving the
pinctrl_enet1_phy_rst from the fec1 node (line 114) to the ethphy0 node
(line 130) appears to apply the pinctrl too late.

Could this cause the PHY reset GPIO pad to remain unconfigured during the
initial MDIO device registration reset sequence? The Linux driver core
applies pinctrl state just before the device probe binds. However, the
MDIO core initial hardware reset pulse happens before the PHY device is
added and bound to a driver. Since the i.MX pinctrl driver does not
implement gpio_request_enable, requesting the GPIO does not automatically
mux the pin in hardware, causing the reset pulse to be swallowed and
leading to initialization failures on cold boots.

[Severity: Medium]
In arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi, the previous
phy-reset-duration on the fec1 node at line 118 was 25 milliseconds. The
new reset-assert-us and reset-deassert-us properties on the ethphy0 node
at line 137 are 500 microseconds.

Can this 50x reduction in reset duration violate the PHY hardware timing
requirements and cause intermittent link negotiation failures? It looks
like the units might have been confused between milliseconds and
microseconds when migrating these properties.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261004140123.46461-1-wahrenst@gmx.net?part=2