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From: Richard Leitner <richard.leitner@linux.dev>
To: Shenwei Wang <shenwei.wang@nxp.com>,
	David Wolfson <wolfson.sol@gmail.com>
Cc: "imx@lists.linux.dev" <imx@lists.linux.dev>
Subject: Re: [EXT] I2C_IMX support for i.MX8MP
Date: Mon, 29 Aug 2022 09:00:30 +0200	[thread overview]
Message-ID: <YwxkDuFgXrsp02R3@skidata.com> (raw)
In-Reply-To: <Yv5C61+2eLgtTvE5@skidata.com>

Hi Shenwei, Hi David,

friendly ping.

On Thu, Aug 18, 2022 at 03:47:23PM +0200, Richard Leitner wrote:
> On Thu, Aug 18, 2022 at 07:54:04AM -0500, David Wolfson wrote:
> > On Thu, Aug 18, 2022 at 11:59:41AM +0000, Shenwei Wang wrote:
> > > Hi Richard,
> > > 
> > > Nothing is hidden here. That is PAD control register, and should be documented in the IOMUXC and PIN Control section in the RM.
> > > 
> > 
> > Checking the IOMUX and PADs' settings is the first step when enabling
> > an interface.
> 
> Sure, that's what I've done. Nonetheless the "8.2.4.280
> SW_PAD_CTL_PAD_I2C3_SCL SW PAD Control Register
> (IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL)" section in the IMX8MPRM says bit 30 is
> reserved.
> 
> So does "8.2.4.128 SW_MUX_CTL_PAD_I2C3_SCL SW MUX Control Register
> (IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL)".
> 
> Maybe I'm just too dumb do find it... So it would be really helpful if
> you could please give a pointer where to find that documentation?

Any hints on where to find the documentation of that bit?

Thanks & regards;rl

      reply	other threads:[~2022-08-29  7:07 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-17 10:38 I2C_IMX support for i.MX8MP Richard Leitner
2022-08-17 14:01 ` [EXT] " Shenwei Wang
2022-08-17 14:07   ` Richard Leitner
2022-08-17 14:14     ` Shenwei Wang
2022-08-18  6:55       ` Richard Leitner
2022-08-18  8:40       ` Richard Leitner
2022-08-18 11:59         ` Shenwei Wang
2022-08-18 12:54           ` David Wolfson
2022-08-18 13:47             ` Richard Leitner
2022-08-29  7:00               ` Richard Leitner [this message]

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