* [PATCH] arm64: dts: s32g: add the eDMA nodes
@ 2025-01-30 7:29 Larisa Grigore
2025-01-30 8:48 ` Krzysztof Kozlowski
0 siblings, 1 reply; 3+ messages in thread
From: Larisa Grigore @ 2025-01-30 7:29 UTC (permalink / raw)
To: Frank Li, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Peng Fan
Cc: imx, dmaengine, devicetree, linux-kernel, s32, Christophe Lizzi,
Alberto Ruiz, Enric Balletbo, Larisa Grigore
Add the two eDMA nodes in the device tree in order to enable the probing
of the S32G2/S32G3 eDMA driver.
Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 34 ++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/s32g3.dtsi | 34 ++++++++++++++++++++++++
2 files changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 7be430b78c83..f73cd5a0906d 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -317,6 +317,23 @@ usdhc0-200mhz-grp4 {
};
};
+ edma0: dma-controller@40144000 {
+ #dma-cells = <2>;
+ compatible = "nxp,s32g2-edma";
+ reg = <0x40144000 0x24000>,
+ <0x4012c000 0x3000>,
+ <0x40130000 0x3000>;
+ dma-channels = <32>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-0-15",
+ "tx-16-31",
+ "err";
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&clks 63>, <&clks 64>;
+ };
+
uart0: serial@401c8000 {
compatible = "nxp,s32g2-linflexuart",
"fsl,s32v234-linflexuart";
@@ -333,6 +350,23 @@ uart1: serial@401cc000 {
status = "disabled";
};
+ edma1: dma-controller@40244000 {
+ #dma-cells = <2>;
+ compatible = "nxp,s32g2-edma";
+ reg = <0x40244000 0x24000>,
+ <0x4022c000 0x3000>,
+ <0x40230000 0x3000>;
+ dma-channels = <32>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-0-15",
+ "tx-16-31",
+ "err";
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&clks 63>, <&clks 64>;
+ };
+
uart2: serial@402bc000 {
compatible = "nxp,s32g2-linflexuart",
"fsl,s32v234-linflexuart";
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index 6c572ffe37ca..ca8b50196ceb 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -374,6 +374,23 @@ usdhc0-200mhz-grp4 {
};
};
+ edma0: dma-controller@40144000 {
+ #dma-cells = <2>;
+ compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
+ reg = <0x40144000 0x24000>,
+ <0x4012c000 0x3000>,
+ <0x40130000 0x3000>;
+ dma-channels = <32>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-0-15",
+ "tx-16-31",
+ "err";
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&clks 63>, <&clks 64>;
+ };
+
uart0: serial@401c8000 {
compatible = "nxp,s32g3-linflexuart",
"fsl,s32v234-linflexuart";
@@ -390,6 +407,23 @@ uart1: serial@401cc000 {
status = "disabled";
};
+ edma1: dma-controller@40244000 {
+ #dma-cells = <2>;
+ compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
+ reg = <0x40244000 0x24000>,
+ <0x4022c000 0x3000>,
+ <0x40230000 0x3000>;
+ dma-channels = <32>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-0-15",
+ "tx-16-31",
+ "err";
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&clks 63>, <&clks 64>;
+ };
+
uart2: serial@402bc000 {
compatible = "nxp,s32g3-linflexuart",
"fsl,s32v234-linflexuart";
--
2.47.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] arm64: dts: s32g: add the eDMA nodes
2025-01-30 7:29 [PATCH] arm64: dts: s32g: add the eDMA nodes Larisa Grigore
@ 2025-01-30 8:48 ` Krzysztof Kozlowski
2025-02-03 7:57 ` Larisa Ileana Grigore
0 siblings, 1 reply; 3+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-30 8:48 UTC (permalink / raw)
To: Larisa Grigore, Frank Li, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Peng Fan
Cc: imx, dmaengine, devicetree, linux-kernel, s32, Christophe Lizzi,
Alberto Ruiz, Enric Balletbo
On 30/01/2025 08:29, Larisa Grigore wrote:
> Add the two eDMA nodes in the device tree in order to enable the probing
> of the S32G2/S32G3 eDMA driver.
>
> Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 34 ++++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 34 ++++++++++++++++++++++++
> 2 files changed, 68 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 7be430b78c83..f73cd5a0906d 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -317,6 +317,23 @@ usdhc0-200mhz-grp4 {
> };
> };
>
> + edma0: dma-controller@40144000 {
> + #dma-cells = <2>;
Any reason for not following DTS coding style in order of properties?
This is odd style.
> + compatible = "nxp,s32g2-edma";
> + reg = <0x40144000 0x24000>,
> + <0x4012c000 0x3000>,
> + <0x40130000 0x3000>;
> + dma-channels = <32>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "tx-0-15",
> + "tx-16-31",
> + "err";
> + clock-names = "dmamux0", "dmamux1";
> + clocks = <&clks 63>, <&clks 64>;
> + };
> +
> uart0: serial@401c8000 {
> compatible = "nxp,s32g2-linflexuart",
> "fsl,s32v234-linflexuart";
> @@ -333,6 +350,23 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + edma1: dma-controller@40244000 {
> + #dma-cells = <2>;
> + compatible = "nxp,s32g2-edma";
> + reg = <0x40244000 0x24000>,
> + <0x4022c000 0x3000>,
> + <0x40230000 0x3000>;
> + dma-channels = <32>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "tx-0-15",
> + "tx-16-31",
> + "err";
interrupts, then interrupt-names but:
> + clock-names = "dmamux0", "dmamux1";
> + clocks = <&clks 63>, <&clks 64>;
here reversed.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] arm64: dts: s32g: add the eDMA nodes
2025-01-30 8:48 ` Krzysztof Kozlowski
@ 2025-02-03 7:57 ` Larisa Ileana Grigore
0 siblings, 0 replies; 3+ messages in thread
From: Larisa Ileana Grigore @ 2025-02-03 7:57 UTC (permalink / raw)
To: Krzysztof Kozlowski, Frank Li, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Peng Fan
Cc: imx, dmaengine, devicetree, linux-kernel, s32, Christophe Lizzi,
Alberto Ruiz, Enric Balletbo
On 1/30/2025 10:48 AM, Krzysztof Kozlowski wrote:
> On 30/01/2025 08:29, Larisa Grigore wrote:
>> Add the two eDMA nodes in the device tree in order to enable the probing
>> of the S32G2/S32G3 eDMA driver.
>>
>> Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
>> ---
>> arch/arm64/boot/dts/freescale/s32g2.dtsi | 34 ++++++++++++++++++++++++
>> arch/arm64/boot/dts/freescale/s32g3.dtsi | 34 ++++++++++++++++++++++++
>> 2 files changed, 68 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
>> index 7be430b78c83..f73cd5a0906d 100644
>> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
>> @@ -317,6 +317,23 @@ usdhc0-200mhz-grp4 {
>> };
>> };
>>
>> + edma0: dma-controller@40144000 {
>> + #dma-cells = <2>;
>
> Any reason for not following DTS coding style in order of properties?
> This is odd style.
>
>> + compatible = "nxp,s32g2-edma";
>> + reg = <0x40144000 0x24000>,
>> + <0x4012c000 0x3000>,
>> + <0x40130000 0x3000>;
>> + dma-channels = <32>;
>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "tx-0-15",
>> + "tx-16-31",
>> + "err";
>> + clock-names = "dmamux0", "dmamux1";
>> + clocks = <&clks 63>, <&clks 64>;
>> + };
>> +
>> uart0: serial@401c8000 {
>> compatible = "nxp,s32g2-linflexuart",
>> "fsl,s32v234-linflexuart";
>> @@ -333,6 +350,23 @@ uart1: serial@401cc000 {
>> status = "disabled";
>> };
>>
>> + edma1: dma-controller@40244000 {
>> + #dma-cells = <2>;
>> + compatible = "nxp,s32g2-edma";
>> + reg = <0x40244000 0x24000>,
>> + <0x4022c000 0x3000>,
>> + <0x40230000 0x3000>;
>> + dma-channels = <32>;
>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "tx-0-15",
>> + "tx-16-31",
>> + "err";
>
> interrupts, then interrupt-names but:
>
>> + clock-names = "dmamux0", "dmamux1";
>> + clocks = <&clks 63>, <&clks 64>;
>
> here reversed.
>
Thank you for your feedback! I will address it in v2.
> Best regards,
> Krzysztof
Best regards,
Larisa
^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-01-30 7:29 [PATCH] arm64: dts: s32g: add the eDMA nodes Larisa Grigore
2025-01-30 8:48 ` Krzysztof Kozlowski
2025-02-03 7:57 ` Larisa Ileana Grigore
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