Re: [PATCH v2 3/5] arm64: dts: imx8qxp: Add MIPI-LVDS combo subsystems

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] dts: simple-pm-bus node specifies address cells but lacks memory-mapped children
- [Low] dts: irqsteer evades DT binding by omitting SoC-specific compatible and power-domains
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commit bf42b82f7a33a44c5f4805e13c2e5eb848f29919
Author: Liu Ying <victor.liu@nxp.com>

arm64: dts: imx8qxp: Add MIPI-LVDS combo subsystems

The MIPI-LVDS combo subsystems are peripherals of pixel link MSI bus in
i.MX8qxp display controller subsystem. Add the MIPI-LVDS combo subsystems.

> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi
> new file mode 100644
> index 0000000000000..67f5392cfc803
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi

[ ... ]

> +&dc0_pl_msi_bus {
> +	mipi_lvds_0_irqsteer: interrupt-controller@56220000 {
> +		compatible = "fsl,imx-irqsteer";

[Severity: Low]
Does this node omit the required SoC-specific compatible and power domains?

The fsl,irqsteer.yaml DT binding schema strictly requires the power-domains
property when the fsl,imx8qxp-irqsteer compatible is used. By only specifying
the generic fsl,imx-irqsteer compatible, this evades the schema's
enforcement.

Failing to model the power domain directly on the interrupt controller violates
the hardware description conventions. The equivalent node in imx8-ss-mipi0.dtsi
correctly included both the SoC-specific compatible and the power-domains
property.

> +		reg = <0x56220000 0x1000>;
> +		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;

[ ... ]

> +	mipi_lvds_0_csr: bus@56221000 {
> +		compatible = "simple-pm-bus", "syscon";
> +		reg = <0x56221000 0x1000>;
> +		clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
> +		clock-names = "ipg";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		mipi_lvds_0_pxl2dpi: pxl2dpi {

[Severity: Low]
Is this simple-pm-bus configuration correct given that it lacks memory-mapped
children?

The mipi_lvds_0_csr node specifies #address-cells = <1> and #size-cells = <1>,
but its children (like pxl2dpi and ldb) do not possess reg properties. The
device tree compiler (dtc) expects children of simple-pm-bus or simple-bus
nodes to have reg properties if #address-cells is greater than 0.

This will trigger simple_bus_reg and avoid_unnecessary_addr_size dtc warnings
during the build and violates standard DT architecture patterns.

> +			compatible = "fsl,imx8qxp-pxl2dpi";
> +			fsl,sc-resource = <IMX_SC_R_MIPI_0>;

[ ... ]

> +	mipi_lvds_1_irqsteer: interrupt-controller@56240000 {
> +		compatible = "fsl,imx-irqsteer";

[Severity: Low]
Like the mipi_lvds_0_irqsteer node above, does this irqsteer node also omit
the fsl,imx8qxp-irqsteer SoC-specific compatible and the power-domains
property?

> +		reg = <0x56240000 0x1000>;
> +		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261014071657.118378-1-alexander.stein@ew.tq-group.com?part=3