Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: "Souza, Jose" <jose.souza@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/adl_p: Implement Wa_22012358565
Date: Wed, 26 May 2021 20:48:23 +0000	[thread overview]
Message-ID: <040ac73b381bd63ad82290ba0078166a52517059.camel@intel.com> (raw)
In-Reply-To: <20210526173600.27708-2-ville.syrjala@linux.intel.com>

On Wed, 2021-05-26 at 20:36 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Implement Wa_22012358565 to avoid underrun with 32bpp cursor
> in some high bandwidth scenarios. The implementation calls for
> overriding the arbitration slots for the planes.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cursor.c   |  4 +++
>  drivers/gpu/drm/i915/display/intel_display.c  |  5 ++++
>  .../drm/i915/display/skl_universal_plane.c    | 27 +++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h               |  8 ++++++
>  4 files changed, 44 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 2ab389b38694..966e020331fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -383,6 +383,10 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
>  	if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
>  		cntl |= MCURSOR_ROTATE_180;
>  
> +	/* Wa_22012358565:adlp */
> +	if (DISPLAY_VER(dev_priv) == 13)
> +		cntl |= MCURSOR_ARB_SLOTS(1);
> +
>  	return cntl;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a2f3d255a906..e23dec8b0aab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -975,6 +975,11 @@ void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
>  		/* FIXME: assert CPU port conditions for SNB+ */
>  	}
>  
> +	/* Wa_22012358565:adlp */
> +	if (DISPLAY_VER(dev_priv) == 13)
> +		intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
> +			     0, PIPE_ARB_USE_PROG_SLOTS);
> +
>  	reg = PIPECONF(cpu_transcoder);
>  	val = intel_de_read(dev_priv, reg);
>  	if (val & PIPECONF_ENABLE) {
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 59e032f3687a..64039f2138c8 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -867,6 +867,29 @@ static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	return plane_ctl;
>  }
>  
> +static int adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state)
> +{
> +	const struct drm_framebuffer *fb = plane_state->hw.fb;
> +
> +	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
> +		switch (fb->format->cpp[0]) {
> +		case 2:
> +			return PLANE_CTL_ARB_SLOTS(1);
> +		default:
> +			return PLANE_CTL_ARB_SLOTS(0);
> +		}
> +	} else {
> +		switch (fb->format->cpp[0]) {
> +		case 8:
> +			return PLANE_CTL_ARB_SLOTS(3);
> +		case 4:
> +			return PLANE_CTL_ARB_SLOTS(1);
> +		default:
> +			return PLANE_CTL_ARB_SLOTS(0);
> +		}
> +	}
> +}
> +
>  static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>  			 const struct intel_plane_state *plane_state)
>  {
> @@ -903,6 +926,10 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>  	else if (key->flags & I915_SET_COLORKEY_SOURCE)
>  		plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
>  
> +	/* Wa_22012358565:adlp */
> +	if (DISPLAY_VER(dev_priv) == 13)
> +		plane_ctl |= adlp_plane_ctl_arb_slots(plane_state);
> +
>  	return plane_ctl;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e4d6336dab71..42f7909fc842 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6146,6 +6146,10 @@ enum {
>  #define  _PIPEBGCMAX           0x71010
>  #define PIPEGCMAX(pipe, i)     _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
>  
> +#define _PIPE_ARB_CTL_A			0x70028 /* icl+ */
> +#define PIPE_ARB_CTL(pipe)		_MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A)
> +#define   PIPE_ARB_USE_PROG_SLOTS	REG_BIT(13)
> +
>  #define _PIPE_MISC_A			0x70030
>  #define _PIPE_MISC_B			0x71030
>  #define   PIPEMISC_YUV420_ENABLE	(1 << 27) /* glk+ */
> @@ -6610,6 +6614,8 @@ enum {
>  #define   MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
>  #define   MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
>  #define   MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
> +#define   MCURSOR_ARB_SLOTS_MASK	REG_GENMASK(30, 28) /* icl+ */
> +#define   MCURSOR_ARB_SLOTS(x)		REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
>  #define   MCURSOR_PIPE_SELECT_MASK	(0x3 << 28)
>  #define   MCURSOR_PIPE_SELECT_SHIFT	28
>  #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
> @@ -7061,6 +7067,8 @@ enum {
>  #define _PLANE_CTL_2_A				0x70280
>  #define _PLANE_CTL_3_A				0x70380
>  #define   PLANE_CTL_ENABLE			(1 << 31)
> +#define   PLANE_CTL_ARB_SLOTS_MASK		REG_GENMASK(30, 28) /* icl+ */
> +#define   PLANE_CTL_ARB_SLOTS(x)		REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
>  #define   PLANE_CTL_PIPE_GAMMA_ENABLE		(1 << 30)   /* Pre-GLK */
>  #define   PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
>  /*

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2021-05-26 20:48 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-26 17:35 [Intel-gfx] [PATCH 1/2] drm/i915/adl_p: Disable FIFO underrun recovery Ville Syrjala
2021-05-26 17:36 ` [Intel-gfx] [PATCH 2/2] drm/i915/adl_p: Implement Wa_22012358565 Ville Syrjala
2021-05-26 20:48   ` Souza, Jose [this message]
2021-05-26 20:33 ` [Intel-gfx] [PATCH 1/2] drm/i915/adl_p: Disable FIFO underrun recovery Souza, Jose
2021-05-26 23:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] " Patchwork
2021-05-27  0:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-27 13:05 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=040ac73b381bd63ad82290ba0078166a52517059.camel@intel.com \
    --to=jose.souza@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=ville.syrjala@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox