Re: [PATCH v1 6/6] drm/i915: Enable Display WA 0528

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
To: Vidya Srinivas <vidya.srinivas@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v1 6/6] drm/i915: Enable Display WA 0528
Date: Wed, 11 Apr 2018 11:39:27 +0200	[thread overview]
Message-ID: <0ce1acf1-85ac-6430-ba66-88b6159b2a5f@linux.intel.com> (raw)
In-Reply-To: <1523437770-14596-7-git-send-email-vidya.srinivas@intel.com>

Op 11-04-18 om 11:09 schreef Vidya Srinivas:
> Possible hang with NV12 plane surface formats.
> WA: When the plane source pixel format is NV12,
> the CHICKEN_PIPESL_* register bit 22 must be set to 1
> and the render decompression must not be enabled
> on any of the planes in that pipe.
The last part is still missing from this patch, you still need to reject CCS fb's?

And this should probably be patch 2.
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++++++++++++++--
>  1 file changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e4cf7a6..71eb49e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -511,12 +511,28 @@ skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
>  		return;
>  
>  	if (enable)
> +		I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);
> +	else
> +		I915_WRITE(CHICKEN_PIPESL_1(pipe), ~HSW_FBCQ_DIS);
You're writing all bits except HSW_FBCQ_DIS here to the chicken register.. I don't think you want that. :)
> +
> +	POSTING_READ(CHICKEN_PIPESL_1(pipe));
> +}
> +
> +static void
> +skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
> +{
> +	if (IS_SKYLAKE(dev_priv))
> +		return;
> +
> +	if (enable)
>  		I915_WRITE(CLKGATE_DIS_PSL(pipe),
>  			   DUPS1_GATING_DIS | DUPS2_GATING_DIS);
>  	else
>  		I915_WRITE(CLKGATE_DIS_PSL(pipe),
>  			   I915_READ(CLKGATE_DIS_PSL(pipe)) &
>  			   ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
> +
> +	POSTING_READ(CLKGATE_DIS_PSL(pipe));
>  }
>  
>  static bool
> @@ -5202,8 +5218,10 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
>  
>  	/* Display WA 827 */
>  	if (needs_nv12_wa(dev_priv, old_crtc_state) &&
> -	    !needs_nv12_wa(dev_priv, pipe_config))
> +	    !needs_nv12_wa(dev_priv, pipe_config)) {
>  		skl_wa_clkgate(dev_priv, crtc->pipe, false);
> +		skl_wa_528(dev_priv, crtc->pipe, false);
> +	}
>  }
>  
>  static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
> @@ -5240,8 +5258,10 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
>  
>  	/* Display WA 827 */
>  	if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
> -	    needs_nv12_wa(dev_priv, pipe_config))
> +	    needs_nv12_wa(dev_priv, pipe_config)) {
>  		skl_wa_clkgate(dev_priv, crtc->pipe, true);
> +		skl_wa_528(dev_priv, crtc->pipe, true);
> +	}
>  
>  	/*
>  	 * Vblank time updates from the shadow to live plane control register


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