From: Chris Wilson <chris@chris-wilson.co.uk>
To: "Zou, Nanhai" <nanhai.zou@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915: SNB BLT workaround
Date: Tue, 02 Nov 2010 10:43:25 +0000 [thread overview]
Message-ID: <0d30dc$k25lhq@orsmga001.jf.intel.com> (raw)
In-Reply-To: <41EFD7A46E18724CAB128DAD0073348018EF55F46B@shsmsx502.ccr.corp.intel.com>
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On Tue, 2 Nov 2010 17:08:09 +0800, "Zou, Nanhai" <nanhai.zou@intel.com> wrote:
> >>-----Original Message-----
> >>From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
> >>Sent: 2010年11月2日 17:05
> >>To: Zou, Nanhai; intel-gfx@lists.freedesktop.org
> >>Cc: Zou, Nanhai
> >>Subject: Re: [PATCH] drm/i915: SNB BLT workaround
> >>
> >>On Tue, 2 Nov 2010 16:31:01 +0800, Zou Nan hai <nanhai.zou@intel.com> wrote:
> >>> on some stepping of SNB cpu, the first command to be parsed in BLT
> >>> command streamer should be MI_BATCHBUFFER_START
> >>> otherwise the GPU may hang.
> >>
> >>Then just add the workaround to the init routine.
> >>-Chris
> >>
>
> The first command here means each BLT command streamer
> begin the parse action, when the ring tail is moving ahead.
Okay, that makes more sense. :)
I added some error checking, then realised that no error checking was done
in 2.6.36 and swore.
Applied to -next and -fixes, with a tag for stable since I presume that
some of these chips were sent to vendors for validation.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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prev parent reply other threads:[~2010-11-02 10:43 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-11-02 8:31 [PATCH] drm/i915: SNB BLT workaround Zou Nan hai
2010-11-02 9:04 ` Chris Wilson
2010-11-02 9:08 ` Zou, Nanhai
2010-11-02 10:43 ` Chris Wilson [this message]
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