From: Zhenyu Wang <zhenyuw@linux.intel.com>
To: eric@anholt.net
Cc: intel-gfx@lists.freedesktop.org
Subject: [PATCH 2/3] agp/intel: add new intel-gtt.h for new GTT controls
Date: Fri, 27 Aug 2010 11:19:18 +0800 [thread overview]
Message-ID: <1282879159-4558-2-git-send-email-zhenyuw@linux.intel.com> (raw)
In-Reply-To: <1282879159-4558-1-git-send-email-zhenyuw@linux.intel.com>
New intel gfx device requires new GTT controls. Add them
into under kernel include dir to be shared with drm/i915
driver.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---
include/linux/intel-gtt.h | 20 ++++++++++++++++++++
1 files changed, 20 insertions(+), 0 deletions(-)
create mode 100644 include/linux/intel-gtt.h
diff --git a/include/linux/intel-gtt.h b/include/linux/intel-gtt.h
new file mode 100644
index 0000000..1d19ab2
--- /dev/null
+++ b/include/linux/intel-gtt.h
@@ -0,0 +1,20 @@
+/*
+ * Common Intel AGPGART and GTT definitions.
+ */
+#ifndef _INTEL_GTT_H
+#define _INTEL_GTT_H
+
+#include <linux/agp_backend.h>
+
+/* This is for Intel only GTT controls.
+ *
+ * Sandybridge: AGP_USER_CACHED_MEMORY default to LLC only
+ */
+
+#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
+#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
+
+/* flag for GFDT type */
+#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
+
+#endif
--
1.7.0.4
next prev parent reply other threads:[~2010-08-27 3:26 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-08-27 3:19 [PATCH 1/3] agp/intel: use #ifdef idiom for intel-agp.h Zhenyu Wang
2010-08-27 3:19 ` Zhenyu Wang [this message]
2010-08-27 3:19 ` [PATCH 3/3] agp/intel: Fix cache control for Sandybridge Zhenyu Wang
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