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From: Zhenyu Wang <zhenyuw@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 2/2] agp/intel: restore cache behavior on sandybridge
Date: Tue,  2 Nov 2010 17:30:47 +0800	[thread overview]
Message-ID: <1288690247-11845-2-git-send-email-zhenyuw@linux.intel.com> (raw)
In-Reply-To: <1288690247-11845-1-git-send-email-zhenyuw@linux.intel.com>

This restores cache behavior for default AGP_USER_MEMORY as
uncached, and leave default AGP_USER_CACHED_MEMORY as LLC only.
I've seen different cache behavior on one sandybridge desktop CPU vs.
another mobile CPU. Until we figure out how to detect the real cache
config, restore back to the original behavior now.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---
 drivers/char/agp/intel-gtt.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 125cd0b..9272c38 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1210,7 +1210,7 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
 	unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
 	u32 pte_flags;
 
-	if (type_mask == AGP_USER_UNCACHED_MEMORY)
+	if (type_mask == AGP_USER_MEMORY)
 		pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
 	else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
 		pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
-- 
1.7.1

  reply	other threads:[~2010-11-02  9:30 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-11-02  9:30 [PATCH 1/2] agp/intel: fix cache control for sandybridge Zhenyu Wang
2010-11-02  9:30 ` Zhenyu Wang [this message]
2010-11-02  9:44   ` [PATCH 2/2] agp/intel: restore cache behavior on sandybridge Chris Wilson

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