From: Harry Wentland <harry.wentland@amd.com>
To: Arun R Murthy <arun.r.murthy@intel.com>,
intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org, jani.nikula@intel.com
Subject: Re: [Intel-gfx] [PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register
Date: Thu, 19 Jan 2023 10:35:02 -0500 [thread overview]
Message-ID: <12bb8690-19a9-dd36-fe05-901e5e889f30@amd.com> (raw)
In-Reply-To: <20230119114707.1425501-1-arun.r.murthy@intel.com>
On 1/19/23 06:47, Arun R Murthy wrote:
> DP2.0 E11 defines a new register to facilitate SDP error detection by a
> 128B/132B capable DPRX device.
>
> v2: Update the macro name to reflect the DP spec(Harry)
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> include/drm/display/drm_dp.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 632376c291db..358db4a9f167 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -692,6 +692,9 @@
> # define DP_FEC_LANE_2_SELECT (2 << 4)
> # define DP_FEC_LANE_3_SELECT (3 << 4)
>
> +#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */
> +#define DP_SDP_CRC16_128B132B_EN BIT(0)
> +
> #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
> # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
>
next prev parent reply other threads:[~2023-01-19 15:35 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-13 4:36 [Intel-gfx] [PATCH 1/2] drm: Add SDP Error Detection Configuration Register Arun R Murthy
2023-01-13 4:36 ` [Intel-gfx] [PATCH 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer Arun R Murthy
2023-01-13 8:19 ` Jani Nikula
2023-01-19 6:19 ` Murthy, Arun R
2023-01-13 5:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm: Add SDP Error Detection Configuration Register Patchwork
2023-01-13 5:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-13 15:57 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-01-13 20:40 ` [Intel-gfx] [PATCH 1/2] " Harry Wentland
2023-01-19 11:47 ` [Intel-gfx] [PATCHv2 " Arun R Murthy
2023-01-19 11:47 ` [Intel-gfx] [PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer Arun R Murthy
2023-01-25 1:58 ` Murthy, Arun R
2023-01-19 15:35 ` Harry Wentland [this message]
2023-01-19 12:57 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [PATCHv2,2/2] i915/display/dp: SDP CRC16 for 128b132b link layer (rev3) Patchwork
2023-01-20 5:59 ` [Intel-gfx] [PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register Arun R Murthy
2023-01-20 5:59 ` [Intel-gfx] [RESEND PATCHv2 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer Arun R Murthy
2023-01-20 6:08 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [RESEND,PATCHv2,2/2] i915/display/dp: SDP CRC16 for 128b132b link layer (rev5) Patchwork
-- strict thread matches above, loose matches on Subject: below --
2023-01-20 6:15 [Intel-gfx] [PATCHv2 0/2] DP2.0 SDP CRC16 for 128/132b link layer Arun R Murthy
2023-02-07 5:26 ` [Intel-gfx] [PATCHv3 " Arun R Murthy
2023-02-07 5:26 ` [Intel-gfx] [PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register Arun R Murthy
2023-02-14 9:34 [Intel-gfx] [PATCHv3 0/2] DP2.0 SDP CRC16 for 128/132b link layer Arun R Murthy
2023-02-14 9:34 ` [Intel-gfx] [PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register Arun R Murthy
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