[RFC] drm/i915: always set positive sync in the sdvo register

[przanoni@gmail.com]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

We use struct intel_sdvo_dtd for that too.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=15766
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42174
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43333

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_sdvo.c |    7 +++----
 1 files changed, 3 insertions(+), 4 deletions(-)


Hi

We have at least 3 reports of wrong sdvo modes that get fixed when we set the
sdvo register to PVSync + PHSync. According to the reporters, modes that contain
NVSync or NHSync don't work without this patch. If you look at the sdvo commnads
(from intel_sdvo_regs.h) you'll see that we also inform the sdvo device about
the positive/negative syncs when we call SDVO_CMD_SET_*_TIMINGS (using the
dtd_flags field of struct intel_sdvo_dtd).

I couldn't find in our documentation any evidence that this patch is actually
right for every sdvo device, but if anyone knows about this or know anyone I
could ask about this, please tell me.

If you have an sdvo device and want to help, please test:
 - use "xrandr --verbose" to check which modes contain -VSync or -HSync or both
 - without this patch, check if modes with -VSync or -HSync or both work (they
   should not be working)
 - apply this patch, and check if all the modes work (they should)
 - if you have newer hardware, be sure to have this patch too before testing
   anything:
   http://lists.freedesktop.org/archives/intel-gfx/2011-October/012726.html

I didn't ask our reporters to test this specific patch, but they're all using
equivalent changes.

Paulo

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 3003fb2..4a6ba9c 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1070,10 +1070,6 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
 			sdvox |= intel_sdvo->color_range;
 		if (INTEL_INFO(dev)->gen < 5)
 			sdvox |= SDVO_BORDER_ENABLE;
-		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
-			sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
-		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
-			sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
 	} else {
 		sdvox = I915_READ(intel_sdvo->sdvo_reg);
 		switch (intel_sdvo->sdvo_reg) {
@@ -1091,6 +1087,9 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
 	if (intel_sdvo->has_hdmi_audio)
 		sdvox |= SDVO_AUDIO_ENABLE;
 
+	/* We already set the {P,N}{V,H}Sync using struct intel_sdvo_dtd */
+	sdvox |= SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
+
 	if (INTEL_INFO(dev)->gen >= 4) {
 		/* done in crtc_mode_set as the dpll_md reg must be written early */
 	} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
-- 
1.7.7.3