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From: ville.syrjala@linux.intel.com
To: dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: [PATCH 12/13] drm/i915: Add post flush DSL readout for surflive debug
Date: Fri, 16 Nov 2012 16:22:24 +0200	[thread overview]
Message-ID: <1353075745-30115-13-git-send-email-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <1353075745-30115-1-git-send-email-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_trace.h   |   19 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_atomic.c |    4 ++++
 2 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index 754a204..fb35edd 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -16,6 +16,25 @@
 
 /* object tracking */
 
+TRACE_EVENT(i915_atomic_flush,
+	    TP_PROTO(u32 dsl0, u32 dsl1, u32 dsl2),
+	    TP_ARGS(dsl0, dsl1, dsl2),
+
+	    TP_STRUCT__entry(
+			     __field(u32, dsl0)
+			     __field(u32, dsl1)
+			     __field(u32, dsl2)
+			     ),
+	    TP_fast_assign(
+			   __entry->dsl0 = dsl0;
+			   __entry->dsl1 = dsl1;
+			   __entry->dsl2 = dsl2;
+			   ),
+
+	    TP_printk("dsl(0)=%u dsl(1)=%u dsl(2)=%u", __entry->dsl0, __entry->dsl1, __entry->dsl2)
+);
+
+
 TRACE_EVENT(i915_atomic_flip,
 	    TP_PROTO(bool sprite, int pipe, int action, u32 commit_surf, u32 commit_surflive, u32 surf, u32 surflive, u32 iir, u32 commit_dsl, u32 dsl, u32 flip_vbl_count, u32 vbl_count),
 	    TP_ARGS(sprite, pipe, action, commit_surf, commit_surflive, surf, surflive, iir, commit_dsl, dsl, flip_vbl_count, vbl_count),
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index c6531b0..945ba75 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -1855,6 +1855,10 @@ static void intel_flip_driver_flush(struct drm_flip_driver *driver)
 	/* Flush posted writes */
 	I915_READ(PIPEDSL(PIPE_A));
 
+#ifdef SURFLIVE_DEBUG
+	trace_i915_atomic_flush(I915_READ(PIPEDSL(0)), I915_READ(PIPEDSL(1)), I915_READ(PIPEDSL(2)));
+#endif
+
 #ifdef FLIP_TIME_DEBUG
 	tend = ktime_get();
 	tdiff = ktime_sub(tend, tstart);
-- 
1.7.8.6

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  parent reply	other threads:[~2012-11-16 14:22 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-11-16 14:22 [PATCH 00/13] drm/i915: Non-blocking GPU synchronization for atomic page flips (v2) ville.syrjala
2012-11-16 14:22 ` [PATCH 01/13] drm/i915: Unstatic i915_gem_check_olr() ville.syrjala
2012-11-16 14:22 ` [PATCH 02/13] drm/i915: Refactor atomic flip code ville.syrjala
2012-11-16 14:22 ` [PATCH 03/13] drm/i915: Implement a non-blocking GPU synchronization mechanism for atomic page flips ville.syrjala
2012-11-16 14:22 ` [PATCH 04/13] drm/i915: Release all atomic flips when GPU hangs ville.syrjala
2012-11-16 14:22 ` [PATCH 05/13] drm/i915: Make a copy of the calculated plane regs ville.syrjala
2012-11-16 14:22 ` [PATCH 06/13] drm/i915: Clear pending flips in haswell_crtc_disable() ville.syrjala
2012-11-16 14:22 ` [PATCH 07/13] drm/i915: Drop all flips waiting for the GPU when the CRTC is about to be disabled ville.syrjala
2012-11-16 14:22 ` [PATCH 08/13] drm/i915: Add pin count trace point ville.syrjala
2012-11-16 14:22 ` [PATCH 09/13] drm/i915: Add trace points for flip queue length ville.syrjala
2012-11-16 14:22 ` [PATCH 10/13] HACK: drm/i915: Make non-blocking GPU synchronization optional ville.syrjala
2012-11-16 14:22 ` [PATCH 11/13] drm/i915: Add some timing debugs to atomic flips ville.syrjala
2012-11-16 14:22 ` ville.syrjala [this message]
2012-11-16 14:22 ` [PATCH 13/13] drm/i915: Add trace point for atomic flip vblank evade ville.syrjala

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