From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 09/10] drm/i915: fix intel_ddi_get_cdclk_freq for ULT machines
Date: Tue, 20 Nov 2012 13:27:43 -0200 [thread overview]
Message-ID: <1353425264-3728-10-git-send-email-przanoni@gmail.com> (raw)
In-Reply-To: <1353425264-3728-1-git-send-email-przanoni@gmail.com>
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
For now, this code is just used by the eDP AUX channel frequency.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_ddi.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 976b470..54a5c10 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1161,6 +1161,8 @@ struct drm_i915_file_private {
#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
+#define IS_ULT(dev) (IS_HASWELL(dev) && \
+ ((dev)->pci_device & 0xFF00) == 0x0A00)
/*
* The genX designation typically refers to the render engine, so render
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index d706d53..852012b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1309,6 +1309,8 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
LCPLL_CLK_FREQ_450)
return 450;
+ else if (IS_ULT(dev_priv->dev))
+ return 338;
else
return 540;
}
--
1.7.11.7
next prev parent reply other threads:[~2012-11-20 15:28 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-20 15:27 [PATCH 00/10] Random Haswell fixes Paulo Zanoni
2012-11-20 15:27 ` [PATCH 01/10] drm/i915: don't limit Haswell CRT encoder to pipe A Paulo Zanoni
2012-11-20 18:20 ` Damien Lespiau
2012-11-20 15:27 ` [PATCH 02/10] drm/i915: fix FDI lane calculation Paulo Zanoni
2012-11-20 18:17 ` Damien Lespiau
2012-11-20 18:43 ` Paulo Zanoni
2012-11-20 15:27 ` [PATCH 03/10] drm/i915: use cpu/pch transcoder on intel_enable_pipe Paulo Zanoni
2012-11-20 18:23 ` Damien Lespiau
2012-11-20 15:27 ` [PATCH 04/10] drm/i915: fix false positive "Unclaimed write" messages Paulo Zanoni
2012-11-20 18:46 ` Damien Lespiau
2012-11-20 19:10 ` Paulo Zanoni
2012-11-20 19:24 ` Damien Lespiau
2012-11-20 19:34 ` Paulo Zanoni
2012-11-20 15:27 ` [PATCH 05/10] drm/i915: make DP work on LPT-LP machines Paulo Zanoni
2012-11-20 16:50 ` Daniel Vetter
2012-11-20 17:12 ` Paulo Zanoni
2012-11-20 19:00 ` Damien Lespiau
2012-11-20 19:14 ` Paulo Zanoni
2012-11-20 15:27 ` [PATCH 06/10] drm/i915: don't intel_crt_init if DDI A has 4 lanes Paulo Zanoni
2012-11-20 19:12 ` Damien Lespiau
2012-11-20 15:27 ` [PATCH 07/10] drm/i915: make the panel fitter work on pipes B and C on IVB Paulo Zanoni
2012-11-20 19:34 ` Damien Lespiau
2012-11-20 15:27 ` [PATCH 08/10] drm/i915: make the panel fitter work on pipes B and C on Haswell Paulo Zanoni
2012-11-20 19:35 ` Damien Lespiau
2012-11-20 15:27 ` Paulo Zanoni [this message]
2012-11-20 19:59 ` [PATCH 09/10] drm/i915: fix intel_ddi_get_cdclk_freq for ULT machines Damien Lespiau
2012-11-20 15:27 ` [PATCH 10/10] drm/i915: implement WaMbcDriverBootEnable on Haswell Paulo Zanoni
2012-11-21 13:31 ` Daniel Vetter
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