From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 4/6] drm/i915: initialize the Haswell SRD interrupts
Date: Wed, 5 Jun 2013 14:21:54 -0300 [thread overview]
Message-ID: <1370452916-3406-5-git-send-email-przanoni@gmail.com> (raw)
In-Reply-To: <1370452916-3406-1-git-send-email-przanoni@gmail.com>
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Same reasons as the other ones: we're not using them so we don't want
them, and this is a preparation for when we enable package C8+ states.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 11 ++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 33f404e..c21055e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2548,11 +2548,14 @@ static void ivybridge_irq_preinstall(struct drm_device *dev)
I915_WRITE(GEN6_PMIER, 0x0);
POSTING_READ(GEN6_PMIER);
- /* Audio */
+ /* Audio and PSR */
if (IS_HASWELL(dev)) {
I915_WRITE(AUDIMR, 0xffffffff);
I915_WRITE(AUDIER, 0x0);
POSTING_READ(AUDIER);
+
+ I915_WRITE(SRDIMR, 0xffffffff);
+ POSTING_READ(SRDIMR);
}
ibx_irq_preinstall(dev);
@@ -2758,6 +2761,9 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
if (IS_HASWELL(dev)) {
I915_WRITE(AUDIIR, I915_READ(AUDIIR));
POSTING_READ(AUDIIR);
+
+ I915_WRITE(SRDIIR, I915_READ(SRDIIR));
+ POSTING_READ(SRDIIR);
}
ibx_irq_postinstall(dev);
@@ -2872,6 +2878,9 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
I915_WRITE(AUDIMR, 0xffffffff);
I915_WRITE(AUDIER, 0x0);
I915_WRITE(AUDIIR, I915_READ(AUDIIR));
+
+ I915_WRITE(SRDIMR, 0xffffffff);
+ I915_WRITE(SRDIIR, I915_READ(SRDIIR));
}
if (HAS_PCH_NOP(dev))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d7f272a..f996e9f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3737,6 +3737,9 @@
#define AUDIIR 0x44088
#define AUDIER 0x4408c
+#define SRDIMR 0x64834
+#define SRDIIR 0x64838
+
#define ILK_DISPLAY_CHICKEN2 0x42004
/* Required on all Ironlake and Sandybridge according to the B-Spec. */
#define ILK_ELPIN_409_SELECT (1 << 25)
--
1.8.1.2
next prev parent reply other threads:[~2013-06-05 17:22 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-05 17:21 [PATCH 0/6] Enable PC8+ states Paulo Zanoni
2013-06-05 17:21 ` [PATCH 1/6] drm/i915: add ibx_irq_preinstall Paulo Zanoni
2013-06-06 11:41 ` Daniel Vetter
2013-06-05 17:21 ` [PATCH 2/6] drm/i915: initialize Haswell audio interrupts Paulo Zanoni
2013-06-05 17:21 ` [PATCH 3/6] drm/i915: initialize FDI RX interrupts Paulo Zanoni
2013-06-05 17:21 ` Paulo Zanoni [this message]
2013-06-05 17:21 ` [PATCH 5/6] drm/i915: initialize the PCH GTC interrupts Paulo Zanoni
2013-06-05 17:21 ` [PATCH 6/6] drm/i915: implement HSW display sequences for package C8+ Paulo Zanoni
2013-06-06 6:49 ` Chris Wilson
2013-06-06 7:40 ` Daniel Vetter
2013-06-12 16:27 ` [PATCH 0/6] Enable PC8+ states Daniel Vetter
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