From: ville.syrjala@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 6/8] drm/i915: Add I915_CACHE_LOCAL to indicate local memory
Date: Thu, 28 Nov 2013 17:15:08 +0200 [thread overview]
Message-ID: <1385651710-7768-7-git-send-email-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <1385651710-7768-1-git-send-email-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
When using local memory, we need to encode the PTEs correctly.
Since cache_mode is the only thing that gets passed down there,
add a new cache_level that's only used for objects allocated from
local memory.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 10 +++++++++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 16 +++++++++++++---
3 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 20a9811..9ee725f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -515,6 +515,7 @@ enum i915_cache_level {
large Last-Level-Cache. LLC is coherent with
the CPU, but L3 is only visible to the GPU. */
I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
+ I915_CACHE_LOCAL, /* local memory */
};
typedef uint32_t gen6_gtt_pte_t;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1bd8953..b08d5d3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1392,7 +1392,8 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
trace_i915_gem_object_fault(obj, page_offset, true, write);
/* Access to snoopable pages through the GTT is incoherent. */
- if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
+ if (obj->cache_level != I915_CACHE_NONE &&
+ obj->cache_level != I915_CACHE_LOCAL && !HAS_LLC(dev)) {
ret = -EINVAL;
goto unlock;
}
@@ -3478,6 +3479,13 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
if (obj->cache_level == cache_level)
return 0;
+ if (obj->cache_level == I915_CACHE_LOCAL) {
+ if (cache_level != I915_CACHE_NONE)
+ return -EINVAL;
+
+ return 0;
+ }
+
if (obj->pin_count) {
DRM_DEBUG("can not change the cache level of pinned objects\n");
return -EBUSY;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 70b148c..0eb6203 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1022,11 +1022,21 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm,
unsigned int pg_start,
enum i915_cache_level cache_level)
{
- unsigned int flags = (cache_level == I915_CACHE_NONE) ?
- AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
+ unsigned int flags;
- intel_gtt_insert_sg_entries(st, pg_start, flags);
+ switch (cache_level) {
+ case I915_CACHE_NONE:
+ flags = AGP_USER_MEMORY;
+ break;
+ case I915_CACHE_LOCAL:
+ flags = AGP_DCACHE_MEMORY;
+ break;
+ default:
+ flags = AGP_USER_CACHED_MEMORY;
+ break;
+ }
+ intel_gtt_insert_sg_entries(st, pg_start, flags);
}
static void i915_ggtt_clear_range(struct i915_address_space *vm,
--
1.8.3.2
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next prev parent reply other threads:[~2013-11-28 15:15 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-28 15:15 [PATCH 0/8] Gen2 stolen/local memory support ville.syrjala
2013-11-28 15:15 ` [PATCH 1/8] x86: Add vfunc for Intel graphics stolen memory base address ville.syrjala
2013-11-28 15:15 ` [PATCH 2/8] x86: Add Intel graphics stolen memory quirk for gen2 platforms ville.syrjala
2013-11-30 12:58 ` Ingo Molnar
2013-11-28 15:15 ` [PATCH 3/8] intel-gtt: Return whether we have local memory or not ville.syrjala
2013-11-28 15:15 ` [PATCH 4/8] intel-gtt: Assume last 128KB of stolen contains the GTT entries on gen2 ville.syrjala
2013-11-28 15:15 ` [PATCH 5/8] intel-gtt: Use i810_write_entry() on gen2 platforms ville.syrjala
2013-11-28 15:15 ` ville.syrjala [this message]
2013-11-28 15:15 ` [PATCH 7/8] drm/i915: Keep track if we have local memory ville.syrjala
2013-11-28 15:15 ` [PATCH 8/8] drm/i915: Determine the stolen memory base address on gen2 ville.syrjala
2013-11-28 16:32 ` Chris Wilson
2013-11-28 18:01 ` Ville Syrjälä
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