[PATCH igt 2/2] Update dpio read/write to take in extra PHY parameter.

[Chon Ming Lee <chon.ming.lee@intel.com>]

The extra parameter is for future platform.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
---
 lib/intel_dpio.c               | 19 +++++++++++++++----
 lib/intel_gpu_tools.h          |  4 ++--
 tools/intel_dpio_read.c        |  2 +-
 tools/intel_dpio_write.c       |  2 +-
 tools/quick_dump/chipset.i     |  4 ++--
 tools/quick_dump/quick_dump.py |  2 +-
 tools/quick_dump/reg_access.py |  6 ++++--
 7 files changed, 26 insertions(+), 13 deletions(-)

diff --git a/lib/intel_dpio.c b/lib/intel_dpio.c
index acfd201..7e22095 100644
--- a/lib/intel_dpio.c
+++ b/lib/intel_dpio.c
@@ -50,12 +50,23 @@ static void intel_display_reg_write(uint32_t reg, uint32_t val)
 	*ptr = val;
 }
 
+static int get_dpio_port(int phy) {
+
+	struct pci_device *dev = intel_get_pci_device();
+	int dpio_port;
+
+	if (IS_VALLEYVIEW(dev->device_id))
+		dpio_port = DPIO_PORTID;
+
+	return dpio_port;
+}
+
 /*
  * In SoCs like Valleyview some of the PLL & Lane control registers
  * can be accessed only through IO side band fabric called DPIO
  */
 uint32_t
-intel_dpio_reg_read(uint32_t reg)
+intel_dpio_reg_read(uint32_t reg, int phy)
 {
 	/* Check whether the side band fabric is ready to accept commands */
 	do {
@@ -64,7 +75,7 @@ intel_dpio_reg_read(uint32_t reg)
 
 	intel_display_reg_write(DPIO_REG, reg);
 	intel_display_reg_write(DPIO_PKT, DPIO_RID |
-						DPIO_OP_READ | DPIO_PORTID | DPIO_BYTE);
+				DPIO_OP_READ | get_dpio_port(phy) | DPIO_BYTE);
 	do {
 		usleep(1);
 	} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
@@ -77,7 +88,7 @@ intel_dpio_reg_read(uint32_t reg)
  * can be accessed only through IO side band fabric called DPIO
  */
 void
-intel_dpio_reg_write(uint32_t reg, uint32_t val)
+intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
 {
 	/* Check whether the side band fabric is ready to accept commands */
 	do {
@@ -87,7 +98,7 @@ intel_dpio_reg_write(uint32_t reg, uint32_t val)
 	intel_display_reg_write(DPIO_DATA, val);
 	intel_display_reg_write(DPIO_REG, reg);
 	intel_display_reg_write(DPIO_PKT, DPIO_RID |
-						DPIO_OP_WRITE | DPIO_PORTID | DPIO_BYTE);
+				DPIO_OP_WRITE | get_dpio_port(phy) | DPIO_BYTE);
 	do {
 		usleep(1);
 	} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
diff --git a/lib/intel_gpu_tools.h b/lib/intel_gpu_tools.h
index 412e465..b242243 100644
--- a/lib/intel_gpu_tools.h
+++ b/lib/intel_gpu_tools.h
@@ -48,8 +48,8 @@ void intel_register_write(uint32_t reg, uint32_t val);
 int intel_register_access_needs_fakewake(void);
 
 /* Following functions are relevant only for SoCs like Valleyview */
-uint32_t intel_dpio_reg_read(uint32_t reg);
-void intel_dpio_reg_write(uint32_t reg, uint32_t val);
+uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
+void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy);
 
 int intel_punit_read(uint8_t addr, uint32_t *val);
 int intel_punit_write(uint8_t addr, uint32_t val);
diff --git a/tools/intel_dpio_read.c b/tools/intel_dpio_read.c
index c0c904a..6202ad9 100644
--- a/tools/intel_dpio_read.c
+++ b/tools/intel_dpio_read.c
@@ -56,7 +56,7 @@ int main(int argc, char** argv)
 
 	intel_register_access_init(dev, 0);
 
-	val = intel_dpio_reg_read(reg);
+	val = intel_dpio_reg_read(reg, 0);
 
 	printf("Read DPIO register: 0x%x - Value : 0x%x\n", reg, val);
 
diff --git a/tools/intel_dpio_write.c b/tools/intel_dpio_write.c
index f842999..3d2f297 100644
--- a/tools/intel_dpio_write.c
+++ b/tools/intel_dpio_write.c
@@ -57,7 +57,7 @@ int main(int argc, char** argv)
 
 	intel_register_access_init(dev, 0);
 
-	intel_dpio_reg_write(reg, val);
+	intel_dpio_reg_write(reg, val, 0);
 
 	intel_register_access_fini();
 
diff --git a/tools/quick_dump/chipset.i b/tools/quick_dump/chipset.i
index f1cc368..c5f4b56 100644
--- a/tools/quick_dump/chipset.i
+++ b/tools/quick_dump/chipset.i
@@ -16,7 +16,7 @@ extern uint32_t intel_register_write(uint32_t reg, uint32_t val);
 extern void intel_register_access_fini();
 extern int intel_register_access_needs_fakewake();
 extern unsigned short pcidev_to_devid(struct pci_device *pci_dev);
-extern uint32_t intel_dpio_reg_read(uint32_t reg);
+extern uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
 %}
 
 extern int is_sandybridge(unsigned short pciid);
@@ -30,4 +30,4 @@ extern uint32_t intel_register_write(uint32_t reg, uint32_t val);
 extern void intel_register_access_fini();
 extern int intel_register_access_needs_fakewake();
 extern unsigned short pcidev_to_devid(struct pci_device *pci_dev);
-extern uint32_t intel_dpio_reg_read(uint32_t reg);
+extern uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
diff --git a/tools/quick_dump/quick_dump.py b/tools/quick_dump/quick_dump.py
index ff151d1..77744d4 100644
--- a/tools/quick_dump/quick_dump.py
+++ b/tools/quick_dump/quick_dump.py
@@ -21,7 +21,7 @@ def parse_file(file):
 	for line in file:
 		register = ast.literal_eval(line)
 		if register[2] == 'DPIO':
-			val = reg.dpio_read(register[1])
+			val = reg.dpio_read(register[1], 0)
 		else:
 			val = reg.read(register[1])
 		intreg = int(register[1], 16)
diff --git a/tools/quick_dump/reg_access.py b/tools/quick_dump/reg_access.py
index 113a3cf..cf6e0a4 100755
--- a/tools/quick_dump/reg_access.py
+++ b/tools/quick_dump/reg_access.py
@@ -27,9 +27,11 @@ def get_wake():
 	mt_forcewake_get()
 	vlv_forcewake_get()
 
-def dpio_read(reg):
+def dpio_read(reg, phy):
 	reg = int(reg, 16)
-	val = chipset.intel_dpio_reg_read(reg)
+	phy = int(phy)
+
+	val = chipset.intel_dpio_reg_read(reg, phy)
 	return val
 
 
-- 
1.8.3.1