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From: ville.syrjala@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/2] drm/i915: Use 32bit read for BB_ADDR
Date: Tue, 10 Dec 2013 20:47:44 +0200	[thread overview]
Message-ID: <1386701265-27747-1-git-send-email-ville.syrjala@linux.intel.com> (raw)

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The BB_ADDR register is documented to be 32bits at least since SNB.
Prior to that the high 32bits were listed as MBZ, so using a 64bit read
doesn't seem worth anything. Also the simulator doesn't like the 64bit
read. So just switch to using a 32bit read instead.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 79dcb8f..9a64292 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -726,7 +726,7 @@ static void i915_record_ring_state(struct drm_device *dev,
 		error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
 		error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
 		if (ring->id == RCS)
-			error->bbaddr = I915_READ64(BB_ADDR);
+			error->bbaddr = I915_READ(BB_ADDR);
 		error->bbstate[ring->id] = I915_READ(RING_BBSTATE(ring->mmio_base));
 	} else {
 		error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
-- 
1.8.3.2

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             reply	other threads:[~2013-12-10 18:47 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-10 18:47 ville.syrjala [this message]
2013-12-10 18:47 ` [PATCH 2/2] drm/i915: Record BB_ADDR for every ring ville.syrjala
2013-12-10 19:36   ` Ben Widawsky
2013-12-10 19:44   ` [PATCH v2 " ville.syrjala
2013-12-11 10:07     ` Daniel Vetter

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