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From: deepak.s@intel.com
To: intel-gfx@lists.freedesktop.org
Cc: Deepak S <deepak.s@intel.com>
Subject: [PATCH v2] drm/i915: Bring UP Power Wells before disabling RC6.
Date: Thu,  9 Jan 2014 19:28:27 +0530	[thread overview]
Message-ID: <1389275907-22354-1-git-send-email-deepak.s@intel.com> (raw)

From: Deepak S <deepak.s@intel.com>

We need do forcewake before Disabling RC6, This is what the BIOS
expects while going into suspend.

v2: updated commit message. (Daniel)

Signed-off-by: Deepak S <deepak.s@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 469170c..bd68eb4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3135,8 +3135,14 @@ static void valleyview_disable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
+	/* we're doing forcewake before Disabling RC6,
+	 * This what the BIOS expects when going into suspend */
+	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
+	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+
 	gen6_disable_rps_interrupts(dev);
 
 	if (dev_priv->vlv_pctx) {
-- 
1.8.4.2

             reply	other threads:[~2014-01-09 13:57 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-01-09 13:58 deepak.s [this message]
2014-01-09 14:02 ` [PATCH v2] drm/i915: Bring UP Power Wells before disabling RC6 Chris Wilson
2014-01-09 15:16   ` S, Deepak

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