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From: Ben Widawsky <benjamin.widawsky@intel.com>
To: Intel GFX <intel-gfx@lists.freedesktop.org>
Subject: [PATCH 3/4] drm/i915/bdw: RPS frequency bits are the same as HSW
Date: Mon, 31 Mar 2014 17:16:43 -0700	[thread overview]
Message-ID: <1396311404-26927-3-git-send-email-benjamin.widawsky@intel.com> (raw)
In-Reply-To: <1396311404-26927-1-git-send-email-benjamin.widawsky@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ed45143..9728c2c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3041,7 +3041,7 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
 	if (val != dev_priv->rps.cur_freq) {
 		gen6_set_rps_thresholds(dev_priv, val);
 
-		if (IS_HASWELL(dev))
+		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 			I915_WRITE(GEN6_RPNSWREQ,
 				   HSW_FREQUENCY(val));
 		else
-- 
1.9.1

  parent reply	other threads:[~2014-04-01  0:16 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-04-01  0:16 [PATCH 1/4] drm/i915/bdw: Set initial rps freq to RP1 Ben Widawsky
2014-04-01  0:16 ` [PATCH 2/4] drm/i915/bdw: Extract rp_state_caps logic Ben Widawsky
2014-04-01  0:16 ` Ben Widawsky [this message]
2014-04-01  7:38   ` [PATCH 3/4] drm/i915/bdw: RPS frequency bits are the same as HSW Daniel Vetter
  -- strict thread matches above, loose matches on Subject: below --
2014-04-01  0:18 [PATCH 1/4] drm/i915/bdw: Set initial rps freq to RP1 Ben Widawsky
2014-04-01  0:18 ` [PATCH 3/4] drm/i915/bdw: RPS frequency bits are the same as HSW Ben Widawsky

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