From: "Souza, Jose" <jose.souza@intel.com>
To: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Yokoyama, Caz" <caz.yokoyama@intel.com>
Cc: "Sripada, Radhakrishna" <radhakrishna.sripada@intel.com>,
"Roper, Matthew D" <matthew.d.roper@intel.com>
Subject: Re: [Intel-gfx] [PATCH 1/1] drm/i915/adlp: Keep hardware default dbox B credits
Date: Wed, 15 Sep 2021 17:17:47 +0000 [thread overview]
Message-ID: <13b95424bc8a4c7c77fe5679f09d4bcdbdb99830.camel@intel.com> (raw)
In-Reply-To: <8b54dd068cbd8b7448a1a2b5b6c6c962f576a6f2.1631725784.git.caz.yokoyama@intel.com>
On Wed, 2021-09-15 at 10:10 -0700, Yokoyama, Caz wrote:
> From: Caz Yokoyama <caz.yokoyama@intel.com>
>
> Do not overwrite registers that don't need to change from default
> value to 0.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> bspec 49213
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a7ca38613f89..9190a3bc28a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2955,18 +2955,23 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> - u32 val;
> + u32 val = intel_de_read(dev_priv, PIPE_MBUS_DBOX_CTL(pipe));
>
> + val &= ~MBUS_DBOX_A_CREDIT_MASK;
> /* Wa_22010947358:adl-p */
> if (IS_ALDERLAKE_P(dev_priv))
> - val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4);
> + val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4);
> else
> - val = MBUS_DBOX_A_CREDIT(2);
> + val |= MBUS_DBOX_A_CREDIT(2);
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (IS_ALDERLAKE_P(dev_priv)) {
> + /* Take effect hardware default MBUS_DBOX_B_CREDIT(8) */
> + } else if (DISPLAY_VER(dev_priv) >= 12) {
> + val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK);
> val |= MBUS_DBOX_BW_CREDIT(2);
> val |= MBUS_DBOX_B_CREDIT(12);
> } else {
> + val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK);
> val |= MBUS_DBOX_BW_CREDIT(1);
> val |= MBUS_DBOX_B_CREDIT(8);
> }
next prev parent reply other threads:[~2021-09-15 17:17 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-15 17:10 [Intel-gfx] [PATCH 1/1] drm/i915/adlp: Keep hardware default dbox B credits Yokoyama, Caz
2021-09-15 17:17 ` Souza, Jose [this message]
2021-09-15 17:56 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/1] " Patchwork
2021-10-05 18:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/1] drm/i915/adlp: Keep hardware default dbox B credits (rev2) Patchwork
2021-10-05 21:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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