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From: ville.syrjala@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/5] drm/i915: Check for FIFO underuns when disabling reporting on gmch platforms
Date: Fri, 16 May 2014 19:40:21 +0300	[thread overview]
Message-ID: <1400258425-32664-2-git-send-email-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <1400258425-32664-1-git-send-email-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

FIFO underruns don't generate an interrupt on gmch platforms, so we
should check whether there were any that we failed to notice when
we're disabling FIFO underrun reporting.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b10fbde..8bb564b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -266,16 +266,22 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev)
 	return true;
 }
 
-static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
+static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
+					     enum pipe pipe, bool enable)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 reg = PIPESTAT(pipe);
-	u32 pipestat = I915_READ(reg) & 0x7fff0000;
+	u32 pipestat = I915_READ(reg) & 0xffff0000;
 
 	assert_spin_locked(&dev_priv->irq_lock);
 
-	I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
-	POSTING_READ(reg);
+	if (enable) {
+		I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
+		POSTING_READ(reg);
+	} else {
+		if (pipestat & PIPE_FIFO_UNDERRUN_STATUS)
+			DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
+	}
 }
 
 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
@@ -432,8 +438,8 @@ bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 
 	intel_crtc->cpu_fifo_underrun_disabled = !enable;
 
-	if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
-		i9xx_clear_fifo_underrun(dev, pipe);
+	if (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
+		i9xx_set_fifo_underrun_reporting(dev, pipe, enable);
 	else if (IS_GEN5(dev) || IS_GEN6(dev))
 		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 	else if (IS_GEN7(dev))
-- 
1.8.5.5

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  reply	other threads:[~2014-05-16 16:40 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-16 16:40 [PATCH 0/5] drm/i915: Some FIFO underrun detection improvements ville.syrjala
2014-05-16 16:40 ` ville.syrjala [this message]
2014-05-21 14:12   ` [PATCH 1/5] drm/i915: Check for FIFO underuns when disabling reporting on gmch platforms Thomas Wood
2014-05-16 16:40 ` [PATCH 2/5] drm/i915: Check for FIFO underruns at the end of modeset on gmch ville.syrjala
2014-05-21 14:12   ` Thomas Wood
2014-05-16 16:40 ` [PATCH 3/5] drm/i915: Convert uncleared FIFO underrun message to errors ville.syrjala
2014-05-16 16:55   ` Daniel Vetter
2014-05-16 16:40 ` [PATCH 4/5] drm/i915: Simplify the uncleared FIFO underrun detection ville.syrjala
2014-05-21 14:13   ` Thomas Wood
2014-05-16 16:40 ` [PATCH 5/5] drm/i915: Shuffle fifo underrun disable/enable points for gmch platforms ville.syrjala
2014-05-21 14:15   ` Thomas Wood
2014-05-21 14:52   ` Daniel Vetter
2014-05-21 14:54     ` Daniel Vetter

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