From: Jani Nikula <jani.nikula@linux.intel.com>
To: Mika Kahola <mika.kahola@intel.com>,
intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: Imre Deak <imre.deak@intel.com>, Mika Kahola <mika.kahola@intel.com>
Subject: Re: [CI 14/32] drm/i915/display: Print additional Cx0 PLL HW state
Date: Tue, 11 Nov 2025 13:14:05 +0200 [thread overview]
Message-ID: <141250547b313dd31f20741af553847f1e2bfa45@intel.com> (raw)
In-Reply-To: <20251031103549.173208-15-mika.kahola@intel.com>
On Fri, 31 Oct 2025, Mika Kahola <mika.kahola@intel.com> wrote:
> From: Imre Deak <imre.deak@intel.com>
>
> Print all the Cx0 PLL state in the PLL state dumper.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 18 +++++++++++++++---
> 1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 3418fc560faf..1e68a73c2ca8 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2311,8 +2311,8 @@ static void intel_c10pll_dump_hw_state(struct intel_display *display,
> unsigned int multiplier, tx_clk_div;
>
> fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
> - drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ",
> - str_yes_no(fracen));
> + drm_dbg_kms(display->drm, "c10pll_hw_state: clock: %d, fracen: %s, ",
> + hw_state->clock, str_yes_no(fracen));
>
> if (fracen) {
> frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
> @@ -2835,7 +2835,7 @@ static void intel_c20pll_dump_hw_state(struct intel_display *display,
> {
> int i;
>
> - drm_dbg_kms(display->drm, "c20pll_hw_state:\n");
> + drm_dbg_kms(display->drm, "c20pll_hw_state clock: %d:\n", hw_state->clock);
> drm_dbg_kms(display->drm,
> "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
> hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
> @@ -2851,12 +2851,24 @@ static void intel_c20pll_dump_hw_state(struct intel_display *display,
> for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
> drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
> hw_state->mplla[i]);
> +
> + /* For full coverage, also print the additional PLL B entry. */
> + WARN_ON(i + 1 != ARRAY_SIZE(hw_state->mpllb));
Why? What if we hit this? At the very least please use
drm_WARN_ON(). What does the comment have to do with the WARN?
> + drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
> }
> +
> + drm_dbg_kms(display->drm, "vdr: custom width: 0x%02x, serdes rate: 0x%02x, hdmi rate: 0x%02x\n",
> + hw_state->vdr.custom_width, hw_state->vdr.serdes_rate, hw_state->vdr.hdmi_rate);
> }
>
> void intel_cx0pll_dump_hw_state(struct intel_display *display,
> const struct intel_cx0pll_state *hw_state)
> {
> + drm_dbg_kms(display->drm,
> + "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10: %s, tbt_mode: %s\n",
> + hw_state->lane_count, str_yes_no(hw_state->ssc_enabled),
> + str_yes_no(hw_state->use_c10), str_yes_no(hw_state->tbt_mode));
> +
> if (hw_state->use_c10)
> intel_c10pll_dump_hw_state(display, &hw_state->c10);
> else
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-11-11 11:14 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-31 10:35 [CI 00/32] [PATCH 00/32] drm/i915/display: Add MTL+ platforms to support dpll framework Mika Kahola
2025-10-31 10:35 ` [CI 01/32] drm/i915/display: Rename TBT functions to be ICL specific Mika Kahola
2025-11-11 5:21 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 02/32] drm/i915/display: Factor out C10 msgbus access start/end helpers Mika Kahola
2025-11-11 5:26 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 03/32] drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag Mika Kahola
2025-11-11 5:29 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables Mika Kahola
2025-11-11 5:36 ` Kandpal, Suraj
2025-11-11 10:02 ` Imre Deak
2025-11-12 4:10 ` Kandpal, Suraj
2025-11-12 12:58 ` Imre Deak
2025-10-31 10:35 ` [CI 05/32] drm/i915/display: Track the C20 PHY VDR state in the PLL state Mika Kahola
2025-11-11 5:43 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 06/32] drm/i915/display: Move definition of Cx0 PHY functions earlier Mika Kahola
2025-11-11 5:45 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 07/32] drm/i915/display: Add macro to get DDI port width from a register value Mika Kahola
2025-11-11 5:47 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 08/32] drm/i915/display: Track the Cx0 PHY enabled lane count in the PLL state Mika Kahola
2025-11-11 5:55 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 09/32] drm/i915/display: Sanitize C10 PHY PLL SSC register setup Mika Kahola
2025-11-11 5:56 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 10/32] drm/i915/display: Read out the Cx0 PHY SSC enabled state Mika Kahola
2025-11-12 4:13 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL state Mika Kahola
2025-11-11 6:08 ` Kandpal, Suraj
2025-11-11 10:11 ` Imre Deak
2025-11-12 4:15 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 12/32] drm/i915/display: Determine Cx0 PLL port clock " Mika Kahola
2025-11-11 6:11 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 13/32] drm/i915/display: Zero Cx0 PLL state before compute and HW readout Mika Kahola
2025-11-11 6:13 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 14/32] drm/i915/display: Print additional Cx0 PLL HW state Mika Kahola
2025-11-11 6:17 ` Kandpal, Suraj
2025-11-11 11:14 ` Jani Nikula [this message]
2025-11-11 11:16 ` Jani Nikula
2025-11-11 12:34 ` Imre Deak
2025-10-31 10:35 ` [CI 15/32] drm/i915/display: Remove state verification Mika Kahola
2025-11-11 6:20 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 16/32] drm/i915/display: PLL information for MTL+ Mika Kahola
2025-11-12 4:19 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 17/32] drm/i915/display: Update C10/C20 state calculation Mika Kahola
2025-11-12 4:28 ` Kandpal, Suraj
2025-11-12 13:52 ` Kahola, Mika
2025-10-31 10:35 ` [CI 18/32] drm/i915/display: Compute plls for MTL+ platform Mika Kahola
2025-11-12 4:41 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 19/32] drm/i915/display: MTL+ .get_dplls Mika Kahola
2025-11-12 4:47 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 20/32] drm/i915/display: MTL+ .put_dplls Mika Kahola
2025-11-12 4:49 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 21/32] drm/i915/display: Add .update_active_dpll Mika Kahola
2025-11-12 4:50 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 22/32] drm/i915/display: Add .update_dpll_ref_clks Mika Kahola
2025-11-12 4:51 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 23/32] drm/i915/display: Add .dump_hw_state Mika Kahola
2025-11-12 5:07 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 24/32] drm/i915/display: Add .compare_hw_state Mika Kahola
2025-11-12 5:10 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 25/32] drm/i915/display: Add .get_hw_state to MTL+ platforms Mika Kahola
2025-11-12 5:14 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 26/32] drm/i915/display: Add .get_freq " Mika Kahola
2025-11-12 5:19 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 27/32] drm/i915/display: Add .crtc_get_dpll hook Mika Kahola
2025-11-12 5:20 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 28/32] drm/i915/display: PLL verify debug state print Mika Kahola
2025-11-12 5:27 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 29/32] drm/i915/display: Add .enable_clock on DDI for MTL+ platforms Mika Kahola
2025-11-12 5:32 ` Kandpal, Suraj
2025-10-31 10:35 ` [CI 30/32] drm/i915/display: Get configuration for C10 and C20 Mika Kahola
2025-10-31 10:35 ` [CI 31/32] drm/i915/display: Add Thunderbolt support Mika Kahola
2025-10-31 10:35 ` [CI 32/32] drm/i915/display: Enable dpll framework for MTL+ Mika Kahola
2025-11-12 5:39 ` Kandpal, Suraj
2025-10-31 15:03 ` ✓ i915.CI.BAT: success for drm/i915/display: Add MTL+ platforms to support dpll framework (rev2) Patchwork
2025-10-31 19:57 ` ✗ i915.CI.Full: failure " Patchwork
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