Re: [PATCH] drm/i915: fix fdi related fifo underruns on hsw

From: Mika Kahola <mika.kahola@intel.com>
To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915: fix fdi related fifo underruns on hsw
Date: Tue, 01 Dec 2015 10:01:55 +0200	[thread overview]
Message-ID: <1448956915.2984.6.camel@sorvi> (raw)
In-Reply-To: <1448705139-12534-1-git-send-email-daniel.vetter@ffwll.ch>

On Sat, 2015-11-28 at 11:05 +0100, Daniel Vetter wrote:
> Similar to
> 
> commit 37ca8d4ccd9860df0747aa2ea281a3c9c4bf8826
> Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Date:   Fri Oct 30 19:20:27 2015 +0200
> 
>     drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB
> 
> we can only enable fifo underrun reporting when using the fdi/lpt
> after everything is set up and after a bit of waiting. The waiting
> is required, enabling it right after enabling encoders will first trigger
> an underrun on the pch and then, 1 frame later, an underrun on the
> cpu. Two vblank waits after encoder enabling seems enough to curb it.
> 
> And similar to
> 
> Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Date:   Fri Nov 20 22:09:18 2015 +0200
> 
>     drm/i915: Suppress spurious CPU FIFO underruns on ILK-IVB
> 
> we also need to make sure cpu fifo underrun reporting is disabled when
> enabling the fdi rx/tx and pch transcoder&port. But somehow this is
> only needed when enabling, not also when disabling.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Tested-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7754db9fa8a4..62097e94996a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4979,7 +4979,11 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  
>  	intel_crtc->active = true;
>  
> -	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> +	if (intel_crtc->config->has_pch_encoder)
> +		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> +	else
> +		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> +
>  	for_each_encoder_on_crtc(dev, crtc, encoder) {
>  		if (encoder->pre_pll_enable)
>  			encoder->pre_pll_enable(encoder);
> @@ -5025,9 +5029,13 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  		intel_opregion_notify_encoder(encoder, true);
>  	}
>  
> -	if (intel_crtc->config->has_pch_encoder)
> +	if (intel_crtc->config->has_pch_encoder) {
> +		intel_wait_for_vblank(dev, pipe);
> +		intel_wait_for_vblank(dev, pipe);
> +		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>  		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
>  						      true);
> +	}
>  
>  	/* If we change the relative order between pipe/planes enabling, we need
>  	 * to change the workaround. */


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