From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH] drm/i915/bxt: Set max cdclk frequency properly
Date: Tue, 5 Apr 2016 14:37:19 -0700 [thread overview]
Message-ID: <1459892239-14041-1-git-send-email-matthew.d.roper@intel.com> (raw)
intel_update_max_cdclk() doesn't have a switch case for Broxton, so
dev_priv->max_cdclk_freq gets set to whatever clock frequency we're
currently running at (e.g., 144 MHz) rather than the true maximum. This
causes our max dotclock to also be set too low and in turn leads mode
verification to reject perfectly valid modes while loading EDID firmware
blobs.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index af74cdb..924d851 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5261,6 +5261,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
dev_priv->max_cdclk_freq = 450000;
else
dev_priv->max_cdclk_freq = 337500;
+ } else if (IS_BROXTON(dev)) {
+ dev_priv->max_cdclk_freq = 624000;
} else if (IS_BROADWELL(dev)) {
/*
* FIXME with extra cooling we can allow
--
2.1.4
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next reply other threads:[~2016-04-05 21:37 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-05 21:37 Matt Roper [this message]
2016-04-05 21:55 ` [PATCH] drm/i915/bxt: Set max cdclk frequency properly Matt Roper
2016-04-06 10:28 ` Ville Syrjälä
2016-04-06 14:17 ` Matt Roper
2016-04-06 17:22 ` Imre Deak
2016-04-06 18:05 ` Matt Roper
2016-04-06 8:30 ` ✗ Fi.CI.BAT: failure for " Patchwork
2016-04-06 17:58 ` Matt Roper
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