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From: Robert Bragg <robert@sixbynine.org>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org,
	Sourab Gupta <sourab.gupta@intel.com>,
	Deepak S <deepak.s@intel.com>,
	Daniel Vetter <daniel.vetter@intel.com>,
	Robert Bragg <robert@sixbynine.org>
Subject: [PATCH 3/9] drm/i915: don't whitelist oacontrol in cmd parser
Date: Wed, 20 Apr 2016 15:23:08 +0100	[thread overview]
Message-ID: <1461162194-1424-4-git-send-email-robert@sixbynine.org> (raw)
In-Reply-To: <1461162194-1424-1-git-send-email-robert@sixbynine.org>

Being able to program OACONTROL from a non-privileged batch buffer is
not sufficient to be able to configure the OA unit. This was originally
allowed to help enable Mesa to expose OA counters via the
INTEL_performance_query extension, but the current implementation based
on programming OACONTROL via a batch buffer isn't able to report useable
data without a more complete OA unit configuration. Mesa handles the
possibility that writes to OACONTROL may not be allowed and so only
advertises the extension after explicitly testing that a write to
OACONTROL succeeds. Based on this; removing OACONTROL from the whitelist
should be ok for userspace.

Removing this simplifies adding a new kernel api for configuring the OA
unit without needing to consider the possibility that userspace might
trample on OACONTROL state which we'd like to start managing within
the kernel instead. In particular running any Mesa based GL application
currently results in clearing OACONTROL when initializing which would
disable the capturing of metrics.

XXX: actually since rebasing this on a recent nightly this patch does
seem to be breaking gnome-shell on mesa-11.1 - it's not clear a.t.m
why the change didn't seem to cause a problem based on v4.5 with the
same gnome-shell/mesa versions.

Signed-off-by: Robert Bragg <robert@sixbynine.org>
---
 drivers/gpu/drm/i915/i915_cmd_parser.c | 33 ++-------------------------------
 1 file changed, 2 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 035f2dd..8d323b9 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -445,7 +445,6 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
 	REG64(PS_INVOCATION_COUNT),
 	REG64(PS_DEPTH_COUNT),
 	REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
-	REG32(GEN7_OACONTROL), /* Only allowed for LRI and SRM. See below. */
 	REG64(MI_PREDICATE_SRC0),
 	REG64(MI_PREDICATE_SRC1),
 	REG32(GEN7_3DPRIM_END_OFFSET),
@@ -1044,8 +1043,7 @@ bool i915_needs_cmd_parser(struct intel_engine_cs *engine)
 static bool check_cmd(const struct intel_engine_cs *engine,
 		      const struct drm_i915_cmd_descriptor *desc,
 		      const u32 *cmd, u32 length,
-		      const bool is_master,
-		      bool *oacontrol_set)
+		      const bool is_master)
 {
 	if (desc->flags & CMD_DESC_REJECT) {
 		DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
@@ -1083,26 +1081,6 @@ static bool check_cmd(const struct intel_engine_cs *engine,
 			}
 
 			/*
-			 * OACONTROL requires some special handling for
-			 * writes. We want to make sure that any batch which
-			 * enables OA also disables it before the end of the
-			 * batch. The goal is to prevent one process from
-			 * snooping on the perf data from another process. To do
-			 * that, we need to check the value that will be written
-			 * to the register. Hence, limit OACONTROL writes to
-			 * only MI_LOAD_REGISTER_IMM commands.
-			 */
-			if (reg_addr == i915_mmio_reg_offset(GEN7_OACONTROL)) {
-				if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
-					DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
-					return false;
-				}
-
-				if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1))
-					*oacontrol_set = (cmd[offset + 1] != 0);
-			}
-
-			/*
 			 * Check the value written to the register against the
 			 * allowed mask/value pair given in the whitelist entry.
 			 */
@@ -1186,7 +1164,6 @@ int i915_parse_cmds(struct intel_engine_cs *engine,
 {
 	u32 *cmd, *batch_base, *batch_end;
 	struct drm_i915_cmd_descriptor default_desc = { 0 };
-	bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */
 	int ret = 0;
 
 	batch_base = copy_batch(shadow_batch_obj, batch_obj,
@@ -1243,8 +1220,7 @@ int i915_parse_cmds(struct intel_engine_cs *engine,
 			break;
 		}
 
-		if (!check_cmd(engine, desc, cmd, length, is_master,
-			       &oacontrol_set)) {
+		if (!check_cmd(engine, desc, cmd, length, is_master)) {
 			ret = -EINVAL;
 			break;
 		}
@@ -1252,11 +1228,6 @@ int i915_parse_cmds(struct intel_engine_cs *engine,
 		cmd += length;
 	}
 
-	if (oacontrol_set) {
-		DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n");
-		ret = -EINVAL;
-	}
-
 	if (cmd >= batch_end) {
 		DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
 		ret = -EINVAL;
-- 
2.7.1

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  parent reply	other threads:[~2016-04-20 14:23 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-20 14:23 [PATCH 0/9] Enable Gen 7 Observation Architecture Robert Bragg
2016-04-20 14:23 ` [PATCH 1/9] drm/i915: Add i915 perf infrastructure Robert Bragg
2016-04-20 22:41   ` Chris Wilson
2016-04-20 14:23 ` [PATCH 2/9] drm/i915: rename OACONTROL GEN7_OACONTROL Robert Bragg
2016-04-20 14:23 ` Robert Bragg [this message]
2016-04-20 14:23 ` [PATCH 4/9] drm/i915: Add 'render basic' Haswell OA unit config Robert Bragg
2016-04-20 14:23 ` [PATCH 5/9] drm/i915: Enable i915 perf stream for Haswell OA unit Robert Bragg
2016-04-20 16:16   ` kbuild test robot
2016-04-20 20:30   ` [Intel-gfx] " kbuild test robot
2016-04-20 21:11   ` Chris Wilson
2016-04-21 16:15     ` Robert Bragg
2016-04-23  8:48       ` Chris Wilson
2016-04-20 22:15   ` Chris Wilson
2016-04-20 22:46   ` Chris Wilson
2016-04-22 11:04     ` Robert Bragg
2016-04-22 11:18       ` Chris Wilson
2016-04-20 22:52   ` Chris Wilson
2016-04-21 15:43     ` Robert Bragg
2016-04-21 16:21       ` Chris Wilson
2016-04-20 23:09   ` Chris Wilson
2016-04-21 15:18     ` Robert Bragg
2016-04-22  1:10       ` Robert Bragg
2016-04-20 23:16   ` Chris Wilson
2016-04-21 15:01     ` Robert Bragg
2016-04-23 10:34   ` Martin Peres
2016-05-03 19:34     ` Robert Bragg
2016-05-03 20:03       ` Robert Bragg
2016-05-04  9:09         ` Martin Peres
2016-05-04  9:49           ` Robert Bragg
2016-05-04 12:24             ` Daniel Vetter
2016-05-04 13:24               ` Robert Bragg
2016-05-04 13:33                 ` Robert Bragg
2016-05-04 13:51                 ` Daniel Vetter
2016-05-04  9:04       ` [Intel-gfx] " Martin Peres
2016-05-04 11:15         ` Robert Bragg
2016-04-20 14:23 ` [PATCH 6/9] drm/i915: advertise available metrics via sysfs Robert Bragg
2016-04-20 14:23 ` [PATCH 7/9] drm/i915: Add dev.i915.perf_event_paranoid sysctl option Robert Bragg
2016-04-20 14:23 ` [PATCH 8/9] drm/i915: add oa_event_min_timer_exponent sysctl Robert Bragg
2016-04-20 14:23 ` [PATCH 9/9] drm/i915: Add more Haswell OA metric sets Robert Bragg
2016-04-20 14:56 ` [PATCH 0/9] Enable Gen 7 Observation Architecture Robert Bragg
2016-04-21  7:46 ` ✓ Fi.CI.BAT: success for Enable Gen 7 Observation Architecture (rev3) Patchwork
2016-04-21 12:41 ` ✗ Fi.CI.BAT: failure " Patchwork
2016-04-23  8:31 ` ✗ Fi.CI.BAT: warning " Patchwork
2016-04-24 17:23 ` ✓ Fi.CI.BAT: success " Patchwork

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