From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Intel-gfx@lists.freedesktop.org
Subject: [RFC 1/3] drm/i915: Use natural width type for VMA pin count
Date: Thu, 21 Apr 2016 13:05:51 +0100 [thread overview]
Message-ID: <1461240353-29576-1-git-send-email-tvrtko.ursulin@linux.intel.com> (raw)
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Using four bits for the pin count in the middle of the data
structure just makes the compiler generate verbose code.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index d7dd3d8a8758..b4766c4c4bac 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -213,9 +213,9 @@ struct i915_vma {
* and the framebuffer code. When switching/pageflipping, the
* framebuffer code has at most two buffers pinned per crtc.
*
- * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
- * bits with absolutely no headroom. So use 4 bits. */
- unsigned int pin_count:4;
+ * In the worst case this is 1 + 1 + 1 + 2*2 = 7.
+ */
+ unsigned int pin_count;
#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
};
--
1.9.1
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next reply other threads:[~2016-04-21 12:05 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-21 12:05 Tvrtko Ursulin [this message]
2016-04-21 12:05 ` [RFC 2/3] drm/i915: Track aggregate per-object VMA pin count Tvrtko Ursulin
2016-04-21 12:15 ` Chris Wilson
2016-04-21 12:53 ` Chris Wilson
2016-04-21 12:05 ` [RFC 3/3] drm/i915: Micro-optimize i915_gem_obj_to_vma Tvrtko Ursulin
2016-04-21 12:17 ` Chris Wilson
2016-04-26 10:35 ` Dave Gordon
2016-04-26 10:45 ` Chris Wilson
2016-04-21 12:16 ` [RFC 1/3] drm/i915: Use natural width type for VMA pin count Chris Wilson
2016-04-23 16:37 ` ✓ Fi.CI.BAT: success for series starting with [RFC,1/3] " Patchwork
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