From: Yetunde Adebisi <yetundex.adebisi@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>, isg-gms@eclists.intel.com
Subject: [PATCH 2/3] drm/i915: Read eDP Display control capability registers
Date: Tue, 26 Apr 2016 12:25:17 +0100 [thread overview]
Message-ID: <1461669918-4851-3-git-send-email-yetundex.adebisi@intel.com> (raw)
In-Reply-To: <1461669918-4851-1-git-send-email-yetundex.adebisi@intel.com>
Add new edp_dpcd variable to intel_dp.
Read and save eDP Display control capability registers to edp_dpcd.
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 15 ++++++++++-----
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f192f58..c12c414 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3714,7 +3714,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- uint8_t rev;
if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
sizeof(intel_dp->dpcd)) < 0)
@@ -3771,6 +3770,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("PSR2 %s on sink",
dev_priv->psr.psr2_support ? "supported" : "not supported");
}
+
+ /* Read the eDP Display control capabilities registers */
+ memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
+ if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+ (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
+ intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
+ sizeof(intel_dp->edp_dpcd)))
+ DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
+ intel_dp->edp_dpcd);
}
DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3778,10 +3786,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
/* Intermediate frequency support */
- if (is_edp(intel_dp) &&
- (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
- (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
- (rev >= 0x03)) { /* eDp v1.4 or higher */
+ if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
int i;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b9f1304..99db8bb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -810,6 +810,7 @@ struct intel_dp {
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
+ uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
uint8_t num_sink_rates;
int sink_rates[DP_MAX_SUPPORTED_RATES];
--
1.9.3
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next prev parent reply other threads:[~2016-04-26 11:25 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-26 11:25 [PATCH 0/3] DPCD Backlight Control Yetunde Adebisi
2016-04-26 11:25 ` [PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size Yetunde Adebisi
2016-04-26 11:25 ` Yetunde Adebisi [this message]
2016-04-26 11:25 ` [PATCH 3/3] drm/i915: Add Backlight Control using DPCD for eDP connectors (v9) Yetunde Adebisi
2016-05-08 16:24 ` Daniel Vetter
-- strict thread matches above, loose matches on Subject: below --
2016-04-05 14:10 [PATCH 0/3] DPCD Backlight Control Yetunde Adebisi
2016-04-05 14:10 ` [PATCH 2/3] drm/i915: Read eDP Display control capability registers Yetunde Adebisi
2016-04-05 13:50 [PATCH 0/3] DPCD Backlight Control Yetunde Adebisi
2016-04-05 13:50 ` [PATCH 2/3] drm/i915: Read eDP Display control capability registers Yetunde Adebisi
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