Re: [PATCH 5/5] drm/i915: Introduce IS_GEN macro

[Joonas Lahtinen <joonas.lahtinen@linux.intel.com>]

On ti, 2016-05-10 at 10:57 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> To be used for more efficient Gen range checking.
> 
> v2: Remove spurious chunk. (Chris Wilson)
> v3: Rebase.
> v4: Renamed from INTEL_GEN_RANGE and added GEN_FOREVER.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v3)

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Dave Gordon <david.s.gordon@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h         | 22 +++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_fbc.c        |  2 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.c |  8 ++++----
>  3 files changed, 26 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6eb26a93bcbb..4393a88c8837 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2519,9 +2519,29 @@ struct drm_i915_cmd_table {
>  #define INTEL_INFO(p) 	(&__I915__(p)->info)
>  #define INTEL_GEN(p)	(INTEL_INFO(p)->gen)
>  #define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
> -#define INTEL_REVID(p)	(__I915__(p)->dev->pdev->revision)
>  
>  #define REVID_FOREVER		0xff
> +#define INTEL_REVID(p)	(__I915__(p)->dev->pdev->revision)
> +
> +#define GEN_FOREVER (0)
> +/*
> + * Returns true if Gen is in inclusive range [Start, End].
> + *
> + * Use GEN_FOREVER for unbound start and or end.
> + */
> +#define IS_GEN(p, s, e) ({ \
> +	unsigned int __s = (s), __e = (e); \
> +	BUILD_BUG_ON(!__builtin_constant_p(s)); \
> +	BUILD_BUG_ON(!__builtin_constant_p(e)); \
> +	if ((__s) != GEN_FOREVER) \
> +		__s = (s) - 1; \
> +	if ((__e) == GEN_FOREVER) \
> +		__e = BITS_PER_LONG - 1; \
> +	else \
> +		__e = (e) - 1; \
> +	!!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
> +})
> +
>  /*
>   * Return true if revision is in range [since,until] inclusive.
>   *
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 4a527d3cf026..0dea5fbcd8aa 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -740,7 +740,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc)
>  
>  	/* FIXME: We lack the proper locking here, so only run this on the
>  	 * platforms that need. */
> -	if (INTEL_INFO(dev_priv)->gen >= 5 && INTEL_INFO(dev_priv)->gen < 7)
> +	if (IS_GEN(dev_priv, 5, 6))
>  		cache->fb.ilk_ggtt_offset = i915_gem_obj_ggtt_offset(obj);
>  	cache->fb.pixel_format = fb->pixel_format;
>  	cache->fb.stride = fb->pitches[0];
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 84b22a57cc1c..0618dd34c3ec 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -506,7 +506,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>  	 * arises: do we still need this and if so how should we go about
>  	 * invalidating the TLB?
>  	 */
> -	if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8) {
> +	if (IS_GEN(dev_priv, 6, 7)) {
>  		i915_reg_t reg = RING_INSTPM(engine->mmio_base);
>  
>  		/* ring should be idle before issuing a sync flush*/
> @@ -1206,7 +1206,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
>  		return ret;
>  
>  	/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
> -	if (INTEL_GEN(dev_priv) >= 4 && INTEL_GEN(dev_priv) < 7)
> +	if (IS_GEN(dev_priv, 4, 6))
>  		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
>  
>  	/* We need to disable the AsyncFlip performance optimisations in order
> @@ -1215,7 +1215,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
>  	 *
>  	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
>  	 */
> -	if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8)
> +	if (IS_GEN(dev_priv, 6, 7))
>  		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
>  
>  	/* Required for the hardware to program scanline values for waiting */
> @@ -1240,7 +1240,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
>  			   _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 6 && INTEL_GEN(dev_priv) < 8)
> +	if (IS_GEN(dev_priv, 6, 7))
>  		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
>  
>  	if (HAS_L3_DPF(dev_priv))
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx