From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Subject: Re: [PATCH 1/8] drm/i915: Flush GT idle status upon reset
Date: Thu, 14 Jul 2016 10:53:20 +0300 [thread overview]
Message-ID: <1468482800.6378.4.camel@linux.intel.com> (raw)
In-Reply-To: <1468397438-21226-1-git-send-email-chris@chris-wilson.co.uk>
On ke, 2016-07-13 at 09:10 +0100, Chris Wilson wrote:
> Upon resetting the GPU, we force the engines to be idle by clearing
> their request lists. However, I neglected to clear the GT active status
> and so the next request following the reset was not marking the device
> as busy again. (We had to wait until any outstanding retire worker
> finally ran and cleared the active status.)
>
> Fixes: 67d97da34917 ("drm/i915: Only start retire worker when idle")
> Testcase: igt/pm_rps/reset
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
No FDO bug associated?
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index adeca0ec4cfb..9d8c26f42dee 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3169,6 +3169,8 @@ static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine)
> }
>
> intel_ring_init_seqno(engine, engine->last_submitted_seqno);
> +
> + engine->i915->gt.active_engines &= ~intel_engine_flag(engine);
> }
>
> void i915_gem_reset(struct drm_device *dev)
> @@ -3186,6 +3188,7 @@ void i915_gem_reset(struct drm_device *dev)
>
> for_each_engine(engine, dev_priv)
> i915_gem_reset_engine_cleanup(engine);
> + mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);
>
> i915_gem_context_reset(dev);
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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next prev parent reply other threads:[~2016-07-14 7:53 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-13 8:10 [PATCH 1/8] drm/i915: Flush GT idle status upon reset Chris Wilson
2016-07-13 8:10 ` [PATCH 2/8] drm/i915: Preserve current RPS frequency across init Chris Wilson
2016-07-13 8:10 ` [PATCH 3/8] drm/i915: Perform static RPS frequency setup before userspace Chris Wilson
2016-07-13 8:10 ` [PATCH 4/8] drm/i915: Move overclocking detection to alongside RPS frequency detection Chris Wilson
2016-07-13 8:10 ` [PATCH 5/8] drm/i915: Define a separate variable and control for RPS waitboost frequency Chris Wilson
2016-07-14 10:26 ` Mika Kuoppala
2016-07-13 8:10 ` [PATCH 6/8] drm/i915: Remove superfluous powersave work flushing Chris Wilson
2016-07-13 8:10 ` [PATCH 7/8] drm/i915: Defer enabling rc6 til after we submit the first batch/context Chris Wilson
2016-07-14 13:56 ` Mika Kuoppala
2016-07-14 14:06 ` Chris Wilson
2016-07-13 8:10 ` [PATCH 8/8] drm/i915: Hide gen6_update_ring_freq() Chris Wilson
2016-07-13 8:48 ` ✗ Ro.CI.BAT: failure for series starting with [1/8] drm/i915: Flush GT idle status upon reset Patchwork
2016-07-13 10:25 ` Mika Kuoppala
2016-07-13 10:30 ` Chris Wilson
2016-07-14 7:53 ` Joonas Lahtinen [this message]
2016-07-14 7:59 ` [PATCH 1/8] " Chris Wilson
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