From: Peter Antoine <peter.antoine@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [I-G-T 2/3] igt/gem_mocs_settings: adding RC6 testings
Date: Fri, 29 Jul 2016 10:34:34 +0100 [thread overview]
Message-ID: <1469784876-33201-3-git-send-email-peter.antoine@intel.com> (raw)
In-Reply-To: <1469784876-33201-1-git-send-email-peter.antoine@intel.com>
This change adds a RC6 test for the MOCS. The MOCS registers are loaded
and saved as part of the RC6 cycle but not all the registers are
saved/restored. This tests that those registers are correctly restored.
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
tests/gem_mocs_settings.c | 56 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/tests/gem_mocs_settings.c b/tests/gem_mocs_settings.c
index 4fb3a02..66d02d9 100644
--- a/tests/gem_mocs_settings.c
+++ b/tests/gem_mocs_settings.c
@@ -518,6 +518,59 @@ static void run_tests(unsigned mode)
intel_register_access_fini();
}
+static unsigned int readit(const char *path)
+{
+ unsigned int ret = 0;
+ int scanned = 0;
+ FILE *file;
+
+ file = fopen(path, "r");
+ igt_assert(file);
+ scanned = fscanf(file, "%u", &ret);
+ igt_assert_eq(scanned, 1);
+
+ fclose(file);
+
+ return ret;
+}
+
+static int read_rc6_residency(void)
+{
+ unsigned int residency;
+ const int device = drm_get_card();
+ static const char path_format[] =
+ "/sys/class/drm/card%d/power/rc6_residency_ms";
+ char path[sizeof(path_format)];
+ int ret;
+
+ ret = snprintf(path, sizeof(path)-1, path_format, device);
+
+ igt_assert_neq(ret, -1);
+ residency = readit(path);
+
+ return residency;
+}
+
+static void context_rc6_test(void)
+{
+ int fd = drm_open_driver(DRIVER_INTEL);
+ int res_ms;
+ uint32_t ctx_id = gem_context_create(fd);
+
+ igt_debug("RC6 Context Test\n");
+ check_control_registers(fd, I915_EXEC_RENDER, ctx_id, false);
+ check_l3cc_registers(fd, I915_EXEC_RENDER, ctx_id, false);
+
+ res_ms = read_rc6_residency();
+ sleep(3);
+ igt_assert_neq(res_ms, read_rc6_residency());
+
+ check_control_registers(fd, I915_EXEC_RENDER, ctx_id, false);
+ check_l3cc_registers(fd, I915_EXEC_RENDER, ctx_id, false);
+ close(fd);
+}
+
+
static void test_requirements(void)
{
int fd = drm_open_driver_master(DRIVER_INTEL);
@@ -537,6 +590,9 @@ igt_main
igt_subtest("mocs-settings")
run_tests(NONE);
+ igt_subtest("mocs-rc6")
+ context_rc6_test();
+
igt_subtest("mocs-reset")
run_tests(RESET);
--
1.9.1
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next prev parent reply other threads:[~2016-07-29 9:34 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-29 9:34 [I-G-T 0/3] igt/gem_mocs_settings: Update MOCS tests Peter Antoine
2016-07-29 9:34 ` [I-G-T 1/3] igt/gem_mocs_settings: Remove direct register tests Peter Antoine
2016-07-29 9:34 ` Peter Antoine [this message]
2016-07-29 9:50 ` [I-G-T 2/3] igt/gem_mocs_settings: adding RC6 testings Antoine, Peter
2016-07-29 9:34 ` [I-G-T 2/3] igt/gem_mocs_settings: adding RC6 tests Peter Antoine
2016-08-01 9:04 ` Chris Wilson
2016-08-01 9:16 ` Peter Antoine
2016-08-01 10:03 ` Peter Antoine
2016-08-01 10:11 ` Chris Wilson
2016-08-01 10:43 ` Peter Antoine
2016-07-29 9:34 ` [I-G-T 3/3] igt/gem_mocs_settings: Reduce the amount of cascading failures Peter Antoine
2016-08-01 9:02 ` Chris Wilson
2016-08-01 9:33 ` Peter Antoine
2016-08-02 14:37 ` Daniel Vetter
2016-08-02 14:47 ` Antoine, Peter
2016-08-03 7:36 ` Daniel Vetter
2016-08-03 8:49 ` Antoine, Peter
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