From: Ramalingam C <ramalingam.c@intel.com>
To: intel-gfx@lists.freedesktop.org, seanpaul@chromium.org
Cc: daniel.vetter@ffwll.ch, rodrigo.vivi@intel.com
Subject: [PATCH 8/8] drm/i915: fix misalignment in HDCP register def
Date: Fri, 2 Feb 2018 16:15:20 +0530 [thread overview]
Message-ID: <1517568320-15579-9-git-send-email-ramalingam.c@intel.com> (raw)
In-Reply-To: <1517568320-15579-1-git-send-email-ramalingam.c@intel.com>
This patch aligns all definitions of hdcp registers and their bits.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 58 ++++++++++++++++++++---------------------
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 65ba10ad1fe5..e9c79b560823 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8483,34 +8483,34 @@ enum skl_power_gate {
#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1<<23)
/* HDCP Key Registers */
-#define HDCP_KEY_CONF _MMIO(0x66c00)
+#define HDCP_KEY_CONF _MMIO(0x66c00)
#define HDCP_AKSV_SEND_TRIGGER BIT(31)
#define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
#define HDCP_KEY_LOAD_TRIGGER BIT(8)
-#define HDCP_KEY_STATUS _MMIO(0x66c04)
-#define HDCP_FUSE_IN_PROGRESS BIT(7)
+#define HDCP_KEY_STATUS _MMIO(0x66c04)
+#define HDCP_FUSE_IN_PROGRESS BIT(7)
#define HDCP_FUSE_ERROR BIT(6)
-#define HDCP_FUSE_DONE BIT(5)
-#define HDCP_KEY_LOAD_STATUS BIT(1)
+#define HDCP_FUSE_DONE BIT(5)
+#define HDCP_KEY_LOAD_STATUS BIT(1)
#define HDCP_KEY_LOAD_DONE BIT(0)
-#define HDCP_AKSV_LO _MMIO(0x66c10)
-#define HDCP_AKSV_HI _MMIO(0x66c14)
+#define HDCP_AKSV_LO _MMIO(0x66c10)
+#define HDCP_AKSV_HI _MMIO(0x66c14)
/* HDCP Repeater Registers */
-#define HDCP_REP_CTL _MMIO(0x66d00)
-#define HDCP_DDIB_REP_PRESENT BIT(30)
-#define HDCP_DDIA_REP_PRESENT BIT(29)
-#define HDCP_DDIC_REP_PRESENT BIT(28)
-#define HDCP_DDID_REP_PRESENT BIT(27)
-#define HDCP_DDIF_REP_PRESENT BIT(26)
-#define HDCP_DDIE_REP_PRESENT BIT(25)
+#define HDCP_REP_CTL _MMIO(0x66d00)
+#define HDCP_DDIB_REP_PRESENT BIT(30)
+#define HDCP_DDIA_REP_PRESENT BIT(29)
+#define HDCP_DDIC_REP_PRESENT BIT(28)
+#define HDCP_DDID_REP_PRESENT BIT(27)
+#define HDCP_DDIF_REP_PRESENT BIT(26)
+#define HDCP_DDIE_REP_PRESENT BIT(25)
#define HDCP_DDIB_SHA1_M0 (1 << 20)
#define HDCP_DDIA_SHA1_M0 (2 << 20)
#define HDCP_DDIC_SHA1_M0 (3 << 20)
#define HDCP_DDID_SHA1_M0 (4 << 20)
#define HDCP_DDIF_SHA1_M0 (5 << 20)
#define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
-#define HDCP_SHA1_BUSY BIT(16)
+#define HDCP_SHA1_BUSY BIT(16)
#define HDCP_SHA1_READY BIT(17)
#define HDCP_SHA1_COMPLETE BIT(18)
#define HDCP_SHA1_V_MATCH BIT(19)
@@ -8526,7 +8526,7 @@ enum skl_power_gate {
#define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
#define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
#define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + h * 4))
-#define HDCP_SHA_TEXT _MMIO(0x66d18)
+#define HDCP_SHA_TEXT _MMIO(0x66d18)
/* HDCP Auth Registers */
#define _PORTA_HDCP_AUTHENC 0x66800
@@ -8542,25 +8542,25 @@ enum skl_power_gate {
_PORTD_HDCP_AUTHENC, \
_PORTE_HDCP_AUTHENC, \
_PORTF_HDCP_AUTHENC) + x)
-#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
-#define HDCP_CONF_CAPTURE_AN BIT(0)
-#define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
-#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
-#define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
-#define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
-#define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
-#define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
-#define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
-#define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
+#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
+#define HDCP_CONF_CAPTURE_AN BIT(0)
+#define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
+#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
+#define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
+#define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
+#define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
+#define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
+#define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
+#define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
#define HDCP_STATUS_STREAM_A_ENC BIT(31)
#define HDCP_STATUS_STREAM_B_ENC BIT(30)
#define HDCP_STATUS_STREAM_C_ENC BIT(29)
#define HDCP_STATUS_STREAM_D_ENC BIT(28)
#define HDCP_STATUS_AUTH BIT(21)
#define HDCP_STATUS_ENC BIT(20)
-#define HDCP_STATUS_RI_MATCH BIT(19)
-#define HDCP_STATUS_R0_READY BIT(18)
-#define HDCP_STATUS_AN_READY BIT(17)
+#define HDCP_STATUS_RI_MATCH BIT(19)
+#define HDCP_STATUS_R0_READY BIT(18)
+#define HDCP_STATUS_AN_READY BIT(17)
#define HDCP_STATUS_CIPHER BIT(16)
#define HDCP_STATUS_FRAME_CNT(x) ((x >> 8) & 0xff)
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2018-02-02 10:51 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-02 10:45 [PATCH 0/8] Adhering to HDCP1.4 Compliance Test Spec Ramalingam C
2018-02-02 10:45 ` [PATCH 1/8] drm/i915: Handle failure from 2nd stage HDCP auth Ramalingam C
2018-02-02 14:09 ` Sean Paul
2018-02-02 14:22 ` Ramalingam C
2018-02-02 14:45 ` Sean Paul
2018-02-02 14:51 ` Ramalingam C
2018-02-02 15:22 ` Sean Paul
2018-02-02 15:26 ` Ramalingam C
2018-02-02 10:45 ` [PATCH 2/8] drm/i915: Stop encryption for repeater with no sink Ramalingam C
2018-02-02 14:13 ` Sean Paul
2018-02-02 14:12 ` Ramalingam C
2018-02-02 14:48 ` Sean Paul
2018-02-02 15:03 ` Ramalingam C
2018-02-02 15:19 ` Sean Paul
2018-02-02 10:45 ` [PATCH 3/8] drm/i915: Connector info in HDCP debug msgs Ramalingam C
2018-02-02 14:15 ` Sean Paul
2018-02-02 10:45 ` [PATCH 4/8] drm/i915: Retry HDCP BKSV read Ramalingam C
2018-02-02 14:16 ` Sean Paul
2018-02-02 14:26 ` Ramalingam C
2018-02-02 14:44 ` Sean Paul
2018-02-02 10:45 ` [PATCH 5/8] drm/i915: Optimize HDCP key load Ramalingam C
2018-02-02 14:18 ` Sean Paul
2018-02-02 14:33 ` Ramalingam C
2018-02-02 15:24 ` Sean Paul
2018-02-02 10:45 ` [PATCH 6/8] drm/i915: Detect panel's hdcp capability Ramalingam C
2018-02-02 14:24 ` Sean Paul
2018-02-02 14:38 ` Ramalingam C
2018-02-02 15:40 ` Sean Paul
2018-02-02 10:45 ` [PATCH 7/8] drm/i915: Reauthenticate HDCP on failure Ramalingam C
2018-02-02 14:37 ` Sean Paul
2018-02-02 15:05 ` Ramalingam C
2018-02-02 10:45 ` Ramalingam C [this message]
2018-02-02 14:38 ` [PATCH 8/8] drm/i915: fix misalignment in HDCP register def Sean Paul
2018-02-02 11:10 ` ✓ Fi.CI.BAT: success for Adhering to HDCP1.4 Compliance Test Spec Patchwork
2018-02-02 12:50 ` ✗ Fi.CI.IGT: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1517568320-15579-9-git-send-email-ramalingam.c@intel.com \
--to=ramalingam.c@intel.com \
--cc=daniel.vetter@ffwll.ch \
--cc=intel-gfx@lists.freedesktop.org \
--cc=rodrigo.vivi@intel.com \
--cc=seanpaul@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox