From: Ramalingam C <ramalingam.c@intel.com>
To: intel-gfx@lists.freedesktop.org, seanpaul@chromium.org,
dri-devel@lists.freedesktop.org
Subject: [PATCH 3/5] drm/i915: Check hdcp key loadability
Date: Mon, 26 Feb 2018 22:42:37 +0530 [thread overview]
Message-ID: <1519665159-28639-4-git-send-email-ramalingam.c@intel.com> (raw)
In-Reply-To: <1519665159-28639-1-git-send-email-ramalingam.c@intel.com>
HDCP1.4 key can be loaded, only when Power well #1 is enabled and cdclk
is enabled. Using the I915 power well infrastruture, above requirement
is verified.
This patch enables the hdcp initialization for HSW, BDW, and BXT.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/intel_hdcp.c | 31 +++++++++++++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 7ea55fa46f41..95081aaa832a 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -37,6 +37,33 @@ static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
return 0;
}
+static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
+{
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_well *power_well;
+ bool enabled = false;
+
+ mutex_lock(&power_domains->lock);
+
+ /* PG1 (power well #1) needs to be enabled */
+ for_each_power_well(dev_priv, power_well) {
+ if (power_well->id == SKL_DISP_PW_1) {
+ enabled = power_well->ops->is_enabled(dev_priv,
+ power_well);
+ break;
+ }
+ }
+ mutex_unlock(&power_domains->lock);
+
+ /*
+ * Another req for hdcp key loadability is enabled state of pll for
+ * cdclk. Without active crtc we wont land here. So we are assuming that
+ * cdclk is already on.
+ */
+
+ return enabled;
+}
+
static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv)
{
I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
@@ -598,8 +625,8 @@ static int _intel_hdcp_enable(struct intel_connector *connector)
DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n",
connector->base.name, connector->base.base.id);
- if (!(I915_READ(SKL_FUSE_STATUS) & SKL_FUSE_PG_DIST_STATUS(1))) {
- DRM_ERROR("PG1 is disabled, cannot load keys\n");
+ if (!hdcp_key_loadable(dev_priv)) {
+ DRM_ERROR("HDCP key Load is not possible\n");
return -ENXIO;
}
--
2.7.4
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next prev parent reply other threads:[~2018-02-26 17:12 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-26 17:12 [PATCH 0/5] HDCP1.4 fixes Ramalingam C
2018-02-26 17:12 ` [PATCH 1/5] drm/i915: Read HDCP R0 thrice in case of mismatch Ramalingam C
2018-02-26 17:37 ` Sean Paul
2018-02-27 11:38 ` Ramalingam C
2018-02-26 17:12 ` [PATCH 2/5] drm/i915: read Vprime thrice incase " Ramalingam C
2018-02-26 17:40 ` Sean Paul
2018-02-27 12:32 ` [PATCH v2] " Ramalingam C
2018-02-26 17:12 ` Ramalingam C [this message]
2018-02-26 17:45 ` [PATCH 3/5] drm/i915: Check hdcp key loadability Sean Paul
2018-02-26 17:12 ` [PATCH 4/5] drm/i915: Poll hdcp register on sudden NACK Ramalingam C
2018-02-26 17:52 ` Sean Paul
2018-02-27 14:36 ` Ramalingam C
2018-02-26 17:12 ` [PATCH 5/5] drm/i915: Move hdcp msg detection into shim Ramalingam C
2018-02-26 18:01 ` Sean Paul
2018-02-27 11:20 ` Ramalingam C
2018-02-26 22:50 ` [Intel-gfx] " Chris Wilson
2018-03-08 6:29 ` Ramalingam C
2018-02-26 17:44 ` ✓ Fi.CI.BAT: success for HDCP1.4 fixes Patchwork
2018-02-26 22:21 ` ✓ Fi.CI.IGT: " Patchwork
2018-02-26 23:24 ` [PATCH 0/5] " Rodrigo Vivi
2018-02-27 11:11 ` Ramalingam C
2018-02-27 13:28 ` ✗ Fi.CI.BAT: failure for HDCP1.4 fixes (rev2) Patchwork
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