From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Fix gen-2 check for 128B tiling
Date: Sat, 21 Jul 2018 16:52:30 -0700 [thread overview]
Message-ID: <1532217150.3997.4.camel@intel.com> (raw)
In-Reply-To: <153216431452.13721.8495414085559421766@skylake-alporthouse-com>
On Sat, 2018-07-21 at 10:11 +0100, Chris Wilson wrote:
> Quoting Dhinakaran Pandiyan (2018-07-21 10:06:07)
> >
> > intel_tile_width_bytes() returns 128B for gen-2 y-tiled buffers
> > while at
> > the same time HAS_128_BYTE_Y_TILING() returns false for gen-2. I am
> > assuming intel_tile_width_bytes() does the right thing.
> >
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> It's rather that gen2 only has 128B tiling. Note that it only makes
> any
> difference for intel_tile_width_bytes()..
Okay, the macro is a bit misleading. Do you have any suggestions to
clarify it or would you prefer I leave it as it is?
> -Chris
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next prev parent reply other threads:[~2018-07-21 23:27 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-21 9:06 [PATCH] drm/i915: Fix gen-2 check for 128B tiling Dhinakaran Pandiyan
2018-07-21 9:11 ` Chris Wilson
2018-07-21 23:52 ` Dhinakaran Pandiyan [this message]
2018-07-21 9:22 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-07-21 9:23 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-21 9:44 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-21 19:52 ` ✓ Fi.CI.IGT: " Patchwork
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