[PATCH] drm/i915/glk: Use cached RCOMP value when re-enabling DPIO Phy

[clinton.a.taylor@intel.com]

From: Clint Taylor <clinton.a.taylor@intel.com>

The calibration RCOMP value in PORT_TX_DW6 in stored in dev_priv during
driver init. Use this value instead of reading the register again as the
power well for PORTA RCOMP register may not be enabled and will return
0xFFFFFFFF instead of the computed value.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
 drivers/gpu/drm/i915/intel_dpio_phy.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 3c7f10d..7cee57f 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -422,8 +422,12 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
 		 * the corresponding calibrated value from PHY1, and disable
 		 * the automatic calibration on PHY0.
 		 */
-		val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
-							  phy_info->rcomp_phy);
+		if (!dev_priv->bxt_phy_grc)
+			val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
+								  phy_info->rcomp_phy);
+		else
+			val = dev_priv->bxt_phy_grc;
+
 		grc_code = val << GRC_CODE_FAST_SHIFT |
 			   val << GRC_CODE_SLOW_SHIFT |
 			   val;
-- 
1.9.1

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