From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com
Subject: [PATCH] drm/i915/icl: Update gamma mode mask
Date: Thu, 21 Feb 2019 00:05:50 +0530 [thread overview]
Message-ID: <1550687750-6730-1-git-send-email-uma.shankar@intel.com> (raw)
Update gamma mode mask to consider even the 30th and 31st
bits as per hardware. Due to this state readout was masking
these bits, causing a mismatch and false warning, even though
the registers were updated correctly. This patch fixes the same.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a5a4736..df1b844 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7142,7 +7142,7 @@ enum {
#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
#define PRE_CSC_GAMMA_ENABLE (1 << 31)
#define POST_CSC_GAMMA_ENABLE (1 << 30)
-#define GAMMA_MODE_MODE_MASK (3 << 0)
+#define GAMMA_MODE_MODE_MASK ((3 << 30) | (3 << 0))
#define GAMMA_MODE_MODE_8BIT (0 << 0)
#define GAMMA_MODE_MODE_10BIT (1 << 0)
#define GAMMA_MODE_MODE_12BIT (2 << 0)
--
1.9.1
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next reply other threads:[~2019-02-20 18:11 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-20 18:35 Uma Shankar [this message]
2019-02-20 18:23 ` [PATCH] drm/i915/icl: Update gamma mode mask Ville Syrjälä
2019-02-20 18:29 ` Shankar, Uma
2019-02-20 18:53 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-02-20 22:29 ` ✓ Fi.CI.IGT: " Patchwork
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