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From: Vidya Srinivas <vidya.srinivas@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] [RFC] drm/vgem: Fix the pitch to be 64 byte aligned for Intel platforms
Date: Tue,  1 Jun 2021 19:58:14 +0530	[thread overview]
Message-ID: <1622557694-9777-1-git-send-email-vidya.srinivas@intel.com> (raw)

User space like igt/kms_prime use vgem_gem_dumb_create
before reaching i915_gem_dumb_create (which has 64 byte alignment done).
For panel resolutions like 1366x768, the pitch calculated by vgem
is not 64 byte aligned. This results in frame buffer not being
created by intel_framebuffer_init.

Test: igt/kms_prime with panel resolution 1366x768

Change-Id: If68914421b1a9432a73af96c8b426045772629eb
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/vgem/vgem_drv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c
index fa54a6d1403d..48535c88aa27 100644
--- a/drivers/gpu/drm/vgem/vgem_drv.c
+++ b/drivers/gpu/drm/vgem/vgem_drv.c
@@ -215,7 +215,7 @@ static int vgem_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 	struct drm_gem_object *gem_object;
 	u64 pitch, size;
 
-	pitch = args->width * DIV_ROUND_UP(args->bpp, 8);
+	pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 	size = args->height * pitch;
 	if (size == 0)
 		return -EINVAL;
-- 
2.7.4

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             reply	other threads:[~2021-06-01 14:37 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-01 14:28 Vidya Srinivas [this message]
2021-06-01 21:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/vgem: Fix the pitch to be 64 byte aligned for Intel platforms Patchwork
2021-06-01 22:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-02  8:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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