Re: [Intel-gfx] [PATCH] drm/i915/adlp+: Disable DC5/6 states for TC port DDI/AUX and for combo port AUX

[Andrzej Hajda <andrzej.hajda@intel.com>]

On 24.04.2023 22:02, Imre Deak wrote:
> On ADLP+ Bspec allows DC5/6 to be enabled while power well 2 is enabled.
> Since the AUX and DDI power wells (except for port A/B) are also backed
> by power well 2, this would suggest that DC5/6 can be enabled while any
> of these AUX or DDI port functionalities are used. As opposed to this
> AUX transfers will time out on ADLP TypeC ports while DC6 is enabled.
> 
> Until the restriction for DC5/6 is clarified in Bspec let's assume that
> the intention is to allow for using these power states while pipe A/B is
> enabled, but only for combo ports which can be used with eDP outputs.
> Similarly assume that AUX transaction initiated by the driver on any port
> requires DC states to be disabled.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Fixes: 88c487938414 ("drm/i915: Use separate "DC off" power well for ADL-P and DG2")
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Great it revives bat-dg2-11.

Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>

Regards
Andrzej

> ---
>   .../i915/display/intel_display_power_map.c    | 28 +++++++++++--------
>   1 file changed, 16 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index 100582f105905..ca448359a8226 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -1251,22 +1251,11 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
>   	POWER_DOMAIN_PIPE_PANEL_FITTER_A,
>   	POWER_DOMAIN_INIT);
>   
> -#define XELPD_PW_2_POWER_DOMAINS \
> -	XELPD_PW_B_POWER_DOMAINS, \
> -	XELPD_PW_C_POWER_DOMAINS, \
> -	XELPD_PW_D_POWER_DOMAINS, \
> -	POWER_DOMAIN_PORT_DDI_LANES_C, \
> -	POWER_DOMAIN_PORT_DDI_LANES_D, \
> -	POWER_DOMAIN_PORT_DDI_LANES_E, \
> +#define XELPD_DC_OFF_PORT_POWER_DOMAINS \
>   	POWER_DOMAIN_PORT_DDI_LANES_TC1, \
>   	POWER_DOMAIN_PORT_DDI_LANES_TC2, \
>   	POWER_DOMAIN_PORT_DDI_LANES_TC3, \
>   	POWER_DOMAIN_PORT_DDI_LANES_TC4, \
> -	POWER_DOMAIN_VGA, \
> -	POWER_DOMAIN_AUDIO_PLAYBACK, \
> -	POWER_DOMAIN_AUX_IO_C, \
> -	POWER_DOMAIN_AUX_IO_D, \
> -	POWER_DOMAIN_AUX_IO_E, \
>   	POWER_DOMAIN_AUX_C, \
>   	POWER_DOMAIN_AUX_D, \
>   	POWER_DOMAIN_AUX_E, \
> @@ -1279,6 +1268,20 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
>   	POWER_DOMAIN_AUX_TBT3, \
>   	POWER_DOMAIN_AUX_TBT4
>   
> +#define XELPD_PW_2_POWER_DOMAINS \
> +	XELPD_PW_B_POWER_DOMAINS, \
> +	XELPD_PW_C_POWER_DOMAINS, \
> +	XELPD_PW_D_POWER_DOMAINS, \
> +	POWER_DOMAIN_PORT_DDI_LANES_C, \
> +	POWER_DOMAIN_PORT_DDI_LANES_D, \
> +	POWER_DOMAIN_PORT_DDI_LANES_E, \
> +	POWER_DOMAIN_VGA, \
> +	POWER_DOMAIN_AUDIO_PLAYBACK, \
> +	POWER_DOMAIN_AUX_IO_C, \
> +	POWER_DOMAIN_AUX_IO_D, \
> +	POWER_DOMAIN_AUX_IO_E, \
> +	XELPD_DC_OFF_PORT_POWER_DOMAINS
> +
>   I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
>   	XELPD_PW_2_POWER_DOMAINS,
>   	POWER_DOMAIN_INIT);
> @@ -1301,6 +1304,7 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
>    */
>   
>   I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
> +	XELPD_DC_OFF_PORT_POWER_DOMAINS,
>   	XELPD_PW_C_POWER_DOMAINS,
>   	XELPD_PW_D_POWER_DOMAINS,
>   	POWER_DOMAIN_PORT_DSI,