From: "Teres Alexis, Alan Previn" <alan.previn.teres.alexis@intel.com>
To: "Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v5 5/7] drm/i915/mtl/huc: auth HuC via GSC
Date: Thu, 1 Jun 2023 23:12:06 +0000 [thread overview]
Message-ID: <1ca14c2cc05eb867fba9ac407f39b0a3734d87d6.camel@intel.com> (raw)
In-Reply-To: <20230531235415.1467475-6-daniele.ceraolospurio@intel.com>
On Wed, 2023-05-31 at 16:54 -0700, Ceraolo Spurio, Daniele wrote:
> The full authentication via the GSC requires an heci packet submission
> to the GSC FW via the GSC CS. The GSC has new PXP command for this
> (literally called NEW_HUC_AUTH).
> The intel_huc_auth function is also updated to handle both authentication
> types.
>
>
alan:snip
> @@ -399,6 +416,9 @@ void intel_huc_fini(struct intel_huc *huc)
> */
> delayed_huc_load_fini(huc);
>
> + if (huc->heci_pkt)
> + i915_vma_unpin_and_release(&huc->heci_pkt, 0);
alan: nit: i just realized that for consistency (init mirror-ing fini), we should be doing this heci releasing after the intel_uc_fw_fini below.
But since the below object isnt referencing the heci packet, this doens't matter, so consider a nit.
alan:snip
> @@ -470,31 +491,41 @@ int intel_huc_auth(struct intel_huc *huc)
> if (!intel_uc_fw_is_loaded(&huc->fw))
> return -ENOEXEC;
>
> - /* GSC will do the auth */
> + /* GSC will do the auth with the load */
> if (intel_huc_is_loaded_by_gsc(huc))
> return -ENODEV;
alan: nit: sorry for another late comment but merely a nit - wondering if we should add a warn in here (to catch
if we could end up here) but its okay - this in theory shouldnt happen anyway.
alan:snip
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
alan:snip
Only a couple of late-comer-nits that you can ignore, else LGTM:
Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
next prev parent reply other threads:[~2023-06-01 23:12 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-31 23:54 [Intel-gfx] [PATCH v5 0/7] drm/i915: HuC loading and authentication for MTL Daniele Ceraolo Spurio
2023-05-31 23:54 ` [Intel-gfx] [PATCH v5 1/7] drm/i915/uc: perma-pin firmwares Daniele Ceraolo Spurio
2023-05-31 23:54 ` [Intel-gfx] [PATCH v5 2/7] drm/i915/huc: Parse the GSC-enabled HuC binary Daniele Ceraolo Spurio
2023-06-01 20:33 ` John Harrison
2023-05-31 23:54 ` [Intel-gfx] [PATCH v5 3/7] drm/i915/huc: Load GSC-enabled HuC via DMA xfer if the fuse says so Daniele Ceraolo Spurio
2023-06-01 20:36 ` John Harrison
2023-06-01 20:42 ` John Harrison
2023-05-31 23:54 ` [Intel-gfx] [PATCH v5 4/7] drm/i915/huc: differentiate the 2 steps of the MTL HuC auth flow Daniele Ceraolo Spurio
2023-06-01 20:40 ` John Harrison
2023-05-31 23:54 ` [Intel-gfx] [PATCH v5 5/7] drm/i915/mtl/huc: auth HuC via GSC Daniele Ceraolo Spurio
2023-06-01 23:12 ` Teres Alexis, Alan Previn [this message]
2023-05-31 23:54 ` [Intel-gfx] [PATCH v5 6/7] drm/i915/mtl/huc: Use the media gt for the HuC getparam Daniele Ceraolo Spurio
2023-05-31 23:54 ` [Intel-gfx] [PATCH v5 7/7] drm/i915/huc: define HuC FW version for MTL Daniele Ceraolo Spurio
2023-06-01 3:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: HuC loading and authentication for MTL (rev7) Patchwork
2023-06-01 3:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-06-01 3:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-06-02 18:24 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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