[PATCH] drm/i915: enable rc6 support on Ironlake

[Jesse Barnes <jbarnes@virtuousgeek.org>]

Doesn't actually work right now, but I did manage to get into rc6 once
and see a lot of power savings (over 1W).
---
 drivers/gpu/drm/i915/i915_reg.h      |    6 ++++++
 drivers/gpu/drm/i915/intel_display.c |   27 +++++++++++++++------------
 2 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d60860e..7f93a13 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -145,6 +145,8 @@
 #define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
 #define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */
 #define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
+#define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
+#define   MI_SUSPEND_FLUSH_EN	(1<<0)
 #define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
 #define MI_OVERLAY_FLIP		MI_INSTR(0x11,0)
 #define   MI_OVERLAY_CONTINUE	(0x0<<21)
@@ -1131,8 +1133,12 @@
 #define RCUPEI			0x111b0
 #define RCDNEI			0x111b4
 #define MCHBAR_RENDER_STANDBY		0x111b8
+#define   RS1_ENABLE		(1<<31)
+#define   RS2_ENABLE		(1<<30)
+#define   RS3_ENABLE		(1<<29)
 #define   RCX_SW_EXIT		(1<<23)
 #define   RSX_STATUS_MASK	0x00700000
+#define   RC_CSTATE_RS2		(3<<4)
 #define VIDCTL			0x111c0
 #define VIDSTS			0x111c8
 #define VIDSTART		0x111cc /* 8 bits */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8806596..eae18ed 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6368,17 +6368,30 @@ void intel_enable_clock_gating(struct drm_device *dev)
 		I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
 	}
 
+	if ((IS_GEN4(dev) || IS_GEN5(dev)) && IS_MOBILE(dev)) {
+		if (dev_priv->pwrctx == NULL)
+			dev_priv->pwrctx = intel_alloc_context_page(dev);
+		if (dev_priv->pwrctx) {
+			struct drm_i915_gem_object *obj = dev_priv->pwrctx;
+			I915_WRITE(PWRCTXA, obj->gtt_offset | PWRCTX_EN);
+			I915_WRITE(MCHBAR_RENDER_STANDBY,
+				   (I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT) | RS1_ENABLE | RS2_ENABLE | RC_CSTATE_RS2);
+		}
+	}
+
 	/*
 	 * GPU can automatically power down the render unit if given a page
 	 * to save state.
 	 */
-	if (IS_IRONLAKE_M(dev) && 0) { /* XXX causes a failure during suspend */
+	if (IS_IRONLAKE_M(dev)) {
 		if (dev_priv->renderctx == NULL)
 			dev_priv->renderctx = intel_alloc_context_page(dev);
 		if (dev_priv->renderctx) {
 			struct drm_i915_gem_object *obj = dev_priv->renderctx;
-			if (BEGIN_LP_RING(4) == 0) {
+			if (BEGIN_LP_RING(6) == 0) {
+				OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
 				OUT_RING(MI_SET_CONTEXT);
+				OUT_RING(MI_SUSPEND_FLUSH);
 				OUT_RING(obj->gtt_offset |
 					 MI_MM_SPACE_GTT |
 					 MI_SAVE_EXT_STATE_EN |
@@ -6393,16 +6406,6 @@ void intel_enable_clock_gating(struct drm_device *dev)
 				       "Disable RC6\n");
 	}
 
-	if (IS_GEN4(dev) && IS_MOBILE(dev)) {
-		if (dev_priv->pwrctx == NULL)
-			dev_priv->pwrctx = intel_alloc_context_page(dev);
-		if (dev_priv->pwrctx) {
-			struct drm_i915_gem_object *obj = dev_priv->pwrctx;
-			I915_WRITE(PWRCTXA, obj->gtt_offset | PWRCTX_EN);
-			I915_WRITE(MCHBAR_RENDER_STANDBY,
-				   I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
-		}
-	}
 }
 
 void intel_disable_clock_gating(struct drm_device *dev)
-- 
1.7.0.4