From: Daniel Vetter <daniel@ffwll.ch>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 0/4] [CFT] interlaced support
Date: Fri, 27 Jan 2012 18:43:06 +0100 [thread overview]
Message-ID: <20120127174306.GE3901@phenom.ffwll.local> (raw)
In-Reply-To: <CA+gsUGScVfzfhhu9gEUHjLTidGyentTomSsqDoi2vi+-fdHDow@mail.gmail.com>
On Fri, Jan 27, 2012 at 02:25:49PM -0200, Paulo Zanoni wrote:
> Ok, so I had to look at the Windows registers again...
>
> Your "interlaced" branch had 6 patches. Patch 3 is the only one I
> changed. Here is my version:
> http://people.freedesktop.org/~pzanoni/0003-drm-i915-fixup-interlace-vertical-timings-confusion.patch.
> Now my monitor reports "1080i" :)
>
> Some notes about the patch:
>
> - I really like your solution of not using CRTC_INTERLACE_HALVE_V,
> because previously we were dividing by 2 and then multiplying by 2
> again, which would not restore the original values in case of odd
> numbers.
>
> - I'm not sure about the change inside drm_modes.c. Why do we need the
> "|= 1"? I fear it could cause us some troubles. This change might also
> break the other drivers, of course. Wel'll need a "v4".
>
> - It seems we need vtotal-- and vblank_end--. We need to find evidence
> for that in the documentation. I'm just copying Windows
>
> - I tested only on SNB. This time the screen looks good (previous
> versions were really ugly). I'll test ilk and report if something goes
> wrong...
I've updated my interlaced branch. Changes:
- Adjust vertical timings as Paulo discovered. I've dropped the change in
drm_mode.c and instead substract one more from vtotal. I hope that this
results in the same configuration.
- Added a paranoia patch to not set unsupported bits on gen2.
- Addes support for vsyncshift. The hw seems to use that to correctly
insert the half-line delay when switching between even and odd fields.
That might also explain why we have to substract a little bit from
vtotal and vblank_end.
Testing feedback highly welcome. And if you can, please compare you
register-settings with those from windows/bios. I'll also add the
VSYNCSHIFT registers to intel_reg_dumper.
Cheers, Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
next prev parent reply other threads:[~2012-01-27 17:43 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-01-26 21:01 [PATCH 0/4] [CFT] interlaced support Daniel Vetter
2012-01-26 21:01 ` [PATCH 1/4] drm/i915: fixup interlaced vertical timings confusion Daniel Vetter
2012-01-26 22:03 ` Chris Wilson
2012-01-26 22:11 ` Daniel Vetter
2012-01-27 19:08 ` Daniel Vetter
2012-01-26 21:01 ` [PATCH 2/4] drm/i915: fixup interlaced support on ilk+ Daniel Vetter
2012-01-26 21:01 ` [PATCH 3/4] drm/i915: allow interlaced mode output on the SDVO connector Daniel Vetter
2012-01-26 21:01 ` [PATCH 4/4] drm/i915: allow interlaced mode output on the HDMI connector Daniel Vetter
2012-01-26 21:38 ` [PATCH 0/4] [CFT] interlaced support Alfonso Fiore
2012-01-26 21:50 ` Daniel Vetter
2012-01-26 22:10 ` Alfonso Fiore
2012-01-26 22:22 ` Daniel Vetter
2012-01-26 23:34 ` Alfonso Fiore
2012-01-27 17:02 ` Daniel Vetter
2012-01-27 17:20 ` Alfonso Fiore
2012-01-26 21:45 ` Paul Menzel
2012-01-27 2:56 ` Paulo Zanoni
2012-01-27 10:22 ` Daniel Vetter
2012-01-27 16:25 ` Paulo Zanoni
2012-01-27 17:43 ` Daniel Vetter [this message]
2012-01-27 21:41 ` Daniel Vetter
2012-01-28 1:52 ` Alfonso Fiore
2012-01-28 11:13 ` Daniel Vetter
2012-01-28 10:21 ` Peter Ross
2012-01-28 10:46 ` Alfonso Fiore
2012-01-28 14:08 ` Daniel Vetter
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