From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: Beeresh G <beeresh.g@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 11/22] drm/i915: Enable DP panel power sequencing for ValleyView
Date: Wed, 28 Mar 2012 16:57:12 -0700 [thread overview]
Message-ID: <20120328165712.204bbe98@jbarnes-desktop> (raw)
In-Reply-To: <20120328215933.GD2046@phenom.ffwll.local>
On Wed, 28 Mar 2012 23:59:33 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:
> On Wed, Mar 28, 2012 at 01:39:31PM -0700, Jesse Barnes wrote:
> > From: Shobhit Kumar <shobhit.kumar@intel.com>
> >
> > VLV supports two dp panels, there are two set of panel power sequence
> > registers which needed to be programmed based on the configured
> > pipe. This patch add supports for the same
> >
> > Acked-by: Acked-by: Ben Widawsky <ben@bwidawsk.net>
> > Signed-off-by: Beeresh G <beeresh.g@intel.com>
> > Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>
> Afaics we use these PP_ regs at tons of other places. Do we not need them
> there or will that follow in a later patch?
> -Daniel
Later patch; this one hasn't been tested yet either.
--
Jesse Barnes, Intel Open Source Technology Center
next prev parent reply other threads:[~2012-03-28 23:57 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-28 20:39 ValleyView patches Jesse Barnes
2012-03-28 20:39 ` [PATCH 01/22] drm/i915: add ValleyView driver structs and IS_VALLEYVIEW macro Jesse Barnes
2012-03-28 20:39 ` [PATCH 02/22] drm/i915: ValleyView watermark support Jesse Barnes
2012-03-28 20:39 ` [PATCH 03/22] drm/i915: PLL defines for VLV Jesse Barnes
2012-03-28 20:39 ` [PATCH 04/22] drm/i915: interrupt bit definitions " Jesse Barnes
2012-03-28 21:33 ` Daniel Vetter
2012-03-28 21:39 ` Jesse Barnes
2012-03-28 21:47 ` Daniel Vetter
2012-03-28 21:50 ` Jesse Barnes
2012-03-28 20:39 ` [PATCH 05/22] drm/i915: add DPIO support Jesse Barnes
2012-03-28 20:39 ` [PATCH 06/22] drm/i915: add ValleyView clock gating init Jesse Barnes
2012-03-28 20:39 ` [PATCH 07/22] drm/i915: split PLL update code out of i9xx_crtc_mode_set Jesse Barnes
2012-03-28 20:39 ` [PATCH 08/22] drm/i915: split LVDS " Jesse Barnes
2012-03-28 20:39 ` [PATCH 09/22] drm/i915: ValleyView mode setting limits and PLL functions Jesse Barnes
2012-03-28 20:39 ` [PATCH 10/22] drm/i915: program drain latency regs on ValleyView Jesse Barnes
2012-03-28 20:39 ` [PATCH 11/22] drm/i915: Enable DP panel power sequencing for ValleyView Jesse Barnes
2012-03-28 21:59 ` Daniel Vetter
2012-03-28 23:57 ` Jesse Barnes [this message]
2012-03-28 20:39 ` [PATCH 12/22] drm/i915: Enable HDMI on ValleyView Jesse Barnes
2012-03-28 20:39 ` [PATCH 13/22] agp/intel: map more registers for use by the GTT code Jesse Barnes
2012-03-28 20:39 ` [PATCH 14/22] agp/intel: add ValleyView AGP driver Jesse Barnes
2012-03-28 20:39 ` [PATCH 15/22] agp/intel: bind " Jesse Barnes
2012-03-28 20:39 ` [PATCH 16/22] drm/i915: add ValleyView specific CRT detect function Jesse Barnes
2012-03-28 20:39 ` [PATCH 17/22] drm/i915: add ValleyView specific force wake get/put functions Jesse Barnes
2012-03-28 20:39 ` [PATCH 18/22] drm/i915: ValleyView IRQ support Jesse Barnes
2012-03-30 16:46 ` Daniel Vetter
2012-03-30 16:52 ` Daniel Vetter
2012-03-28 20:39 ` [PATCH 19/22] drm/i915: check for disabled interrupts on ValleyView Jesse Barnes
2012-03-28 20:39 ` [PATCH 20/22] drm/i915: add HDMI and DP port enumeration " Jesse Barnes
2012-03-28 20:39 ` [PATCH 21/22] drm/i915: disable turbo on ValleyView for now Jesse Barnes
2012-03-28 22:02 ` Daniel Vetter
2012-03-28 23:57 ` Jesse Barnes
2012-03-28 20:39 ` [PATCH 22/22] drm/i915: bind driver to ValleyView chipsets Jesse Barnes
2012-03-29 9:06 ` ValleyView patches Daniel Vetter
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