Re: [PATCH] drm/i915: fix gen4 gpu reset

[Daniel Vetter <daniel@ffwll.ch>]

On Wed, May 02, 2012 at 12:54:46PM -0700, Kenneth Graunke wrote:
> On 05/02/2012 12:33 PM, Daniel Vetter wrote:
> >While trying to fix up gen4 gpu reset in
> >
> >commit f49f0586191fe16140410db0a46d43bdc690d6af
> >Author: Kenneth Graunke<kenneth@whitecape.org>
> >Date:   Sat Sep 11 01:19:14 2010 -0700
> >
> >     drm/i915: Actually set the reset bit in i965_reset
> >
> >a little confusion about when wait_for times out has been introduced -
> >wait for loops _until_ the condition is true.
> >
> >This fixes gpu reset on my gm45, testing with my hangman code shows
> >that it's now fairly reliable - it only died after well over 100 reset
> >cycles.
> >
> >Cc: Kenneth Graunke<kenneth@whitecape.org>
> >Cc: Eric Anholt<eric@anholt.net>
> >Signed-Off-by: Daniel Vetter<daniel.vetter@ffwll.ch>
> >---
> >  drivers/gpu/drm/i915/i915_drv.c |    2 +-
> >  1 files changed, 1 insertions(+), 1 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> >index 133f101..77b7a50 100644
> >--- a/drivers/gpu/drm/i915/i915_drv.c
> >+++ b/drivers/gpu/drm/i915/i915_drv.c
> >@@ -707,7 +707,7 @@ static int i965_reset_complete(struct drm_device *dev)
> >  {
> >  	u8 gdrst;
> >  	pci_read_config_byte(dev->pdev, I965_GDRST,&gdrst);
> >-	return gdrst&  0x1;
> >+	return (gdrst&  GRDOM_RESET_ENABLE) == 0;
> >  }
> >
> >  static int i965_do_reset(struct drm_device *dev)
> 
> How embarassing :)  Ironlake also has the same bug and IIRC hasn't
> been resetting properly for me.  I can test that if you'd like.

Yeah, would be great if you could try to reproduce your ilk reset failure
- it seems to work for me here.

> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
> 
> I might also Cc: stable@kernel.org an equivalent of this...but, up to you.

Well, given that we do not even have a bug report about this regression,
I'll leave this out. Thanks for the review.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48