From: Daniel Vetter <daniel@ffwll.ch>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>,
Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915: properly handle interlaced bit for sdvo dtd conversion
Date: Tue, 22 May 2012 09:24:59 +0200 [thread overview]
Message-ID: <20120522072459.GC4672@phenom.ffwll.local> (raw)
In-Reply-To: <CA+gsUGTUWpRa1Cca6exPvxV1C6C68BgfoU0O5s2Vs8fOdS9kNg@mail.gmail.com>
On Mon, May 21, 2012 at 03:38:34PM -0300, Paulo Zanoni wrote:
> 2012/5/12 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > We've simply ignored this, which isn't too great. With this, interlaced
> > 1080i works on my HDMI screen connected through sdvo. For no apparent
> > reason anything else still doesn't work as it should.
> >
> > While at it, give these magic numbers in the dtd proper names and
> > add a comment that they match with EDID detailed timings.
> >
> > v2: Actually use the right bit for interlaced.
> >
> > Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> This looks like 2 different patches merged into one :)
>
> In theory, bits 2 and 1 could have a different meaning too, but I'm
> not sure how applicable this is to sDVO. But yeah, I had to read this
> code in the past and 0x2 and 0x4 were not exactly nice to read, so at
> least now those bits have a name :)
>
> Not tested, just reviewed against the sdvo and edid specs...
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Picked up for -fixes, thanks for the review.
-Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
prev parent reply other threads:[~2012-05-22 7:23 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-05-12 20:22 [PATCH] drm/i915: properly handle interlaced bit for sdvo dtd conversion Daniel Vetter
2012-05-13 1:52 ` Peter Ross
2012-05-13 13:24 ` Daniel Vetter
2012-05-21 18:38 ` Paulo Zanoni
2012-05-22 7:24 ` Daniel Vetter [this message]
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