From: Ben Widawsky <ben@bwidawsk.net>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/9] drm/i915: disable DOP clock gating on VLV and IVB
Date: Wed, 19 Sep 2012 14:41:31 -0700 [thread overview]
Message-ID: <20120919144131.2156ff3b@bwidawsk.net> (raw)
In-Reply-To: <1348086543-24427-1-git-send-email-jbarnes@virtuousgeek.org>
On Wed, 19 Sep 2012 13:28:55 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> References: https://bugs.freedesktop.org/show_bug.cgi?id=50233
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index a828e90..b89e5f5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3443,6 +3443,7 @@
>
> #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
> #define GEN7_WA_L3_CHICKEN_MODE
> 0x20000000 +#define
> GEN7_WA_DOP_CLOCK_GATING_DISABLE 0x08000000
> /* WaCatErrorRejectionIssue */
> #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c index 36c6409..7ec4b28 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3541,7 +3541,8 @@ static void ivybridge_init_clock_gating(struct
> drm_device *dev) I915_WRITE(GEN7_L3CNTLREG1,
> GEN7_WA_FOR_GEN7_L3_CONTROL);
> I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
> - GEN7_WA_L3_CHICKEN_MODE);
> + GEN7_WA_L3_CHICKEN_MODE |
> + GEN7_WA_DOP_CLOCK_GATING_DISABLE);
>
> /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
> * gating disable must be set. Failure to set it results in
> @@ -3611,7 +3612,8 @@ static void valleyview_init_clock_gating(struct
> drm_device *dev)
> /* WaApplyL3ControlAndL3ChickenMode requires those two on
> Ivy Bridge */ I915_WRITE(GEN7_L3CNTLREG1,
> GEN7_WA_FOR_GEN7_L3_CONTROL);
> - I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
> GEN7_WA_L3_CHICKEN_MODE);
> + I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
> GEN7_WA_L3_CHICKEN_MODE |
> + GEN7_WA_DOP_CLOCK_GATING_DISABLE);
>
> /* This is required by WaCatErrorRejectionIssue */
> I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
As discussed on IRC, can you confirm the register I use in the L3
partity work isn't the right one. You can remove that disabling there
as well with this patch.
--
Ben Widawsky, Intel Open Source Technology Center
next prev parent reply other threads:[~2012-09-19 21:41 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-19 20:28 [PATCH 1/9] drm/i915: disable DOP clock gating on VLV and IVB Jesse Barnes
2012-09-19 20:28 ` [PATCH 2/9] drm/i915: implement WaForceL3Serialization " Jesse Barnes
2012-09-19 20:28 ` [PATCH 3/9] drm/i915: add a HSW scratch location for flush commands Jesse Barnes
2012-09-25 8:54 ` Daniel Vetter
2012-09-25 11:08 ` Jesse Barnes
2012-09-25 11:47 ` Daniel Vetter
2012-09-25 12:08 ` Jesse Barnes
2012-09-19 20:28 ` [PATCH 4/9] drm/i915: add post-flush store dw workaround Jesse Barnes
2012-09-25 8:49 ` Daniel Vetter
2012-09-25 11:07 ` Jesse Barnes
2012-09-19 20:28 ` [PATCH 5/9] drm/i915: implement WaDisableEarlyCull for VLV and IVB Jesse Barnes
2012-09-19 20:29 ` [PATCH 6/9] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB and VLV Jesse Barnes
2012-09-25 8:51 ` Daniel Vetter
2012-10-01 16:52 ` Lespiau, Damien
2012-10-01 16:56 ` Jesse Barnes
2012-10-01 17:07 ` Lespiau, Damien
2012-10-01 16:57 ` Lespiau, Damien
2012-09-19 20:29 ` [PATCH 7/9] drm/i915: limit VLV IRQ enables to those we use Jesse Barnes
2012-09-26 14:16 ` Daniel Vetter
2012-09-19 20:29 ` [PATCH 8/9] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op Jesse Barnes
2012-09-19 20:29 ` [PATCH 9/9] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-09-19 21:41 ` Ben Widawsky [this message]
2012-09-19 22:06 ` [PATCH 1/9] drm/i915: disable DOP clock gating on VLV and IVB Jesse Barnes
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