From: Daniel Vetter <daniel@ffwll.ch>
To: Ben Widawsky <ben@bwidawsk.net>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Valleyview doesn't have rc6+ or rc6++
Date: Wed, 26 Sep 2012 14:06:36 +0200 [thread overview]
Message-ID: <20120926120636.GD1980@bremse> (raw)
In-Reply-To: <1347927015-15553-1-git-send-email-ben@bwidawsk.net>
On Mon, Sep 17, 2012 at 05:10:15PM -0700, Ben Widawsky wrote:
> I do not currently have a VLV to test this on, but hopefully it only
> removes information from debugfs, sysfs, and prevents enabling an
> unsupported mode.
>
> CC: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Haswell seems to have a similar issue ...
-Daniel
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 5 +++++
> drivers/gpu/drm/i915/i915_sysfs.c | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> 3 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 7a4b3f3..4e74a6a 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1144,11 +1144,16 @@ static int gen6_drpc_info(struct seq_file *m)
> I915_READ(GEN6_GT_GFX_RC6_LOCKED));
> seq_printf(m, "RC6 residency since boot: %u\n",
> I915_READ(GEN6_GT_GFX_RC6));
> +
> + if (IS_VALLEYVIEW(dev))
> + goto out;
> +
> seq_printf(m, "RC6+ residency since boot: %u\n",
> I915_READ(GEN6_GT_GFX_RC6p));
> seq_printf(m, "RC6++ residency since boot: %u\n",
> I915_READ(GEN6_GT_GFX_RC6pp));
>
> +out:
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index a253515..4717a42 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -41,6 +41,9 @@ static u32 calc_residency(struct drm_device *dev, const u32 reg)
> if (!intel_enable_rc6(dev))
> return 0;
>
> + if (IS_VALLEYVIEW(dev) && reg != GEN6_GT_GFX_RC6)
> + return 0;
> +
> raw_time = I915_READ(reg) * 128ULL;
> return DIV_ROUND_UP_ULL(raw_time, 100000);
> }
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 82ca172..ccd50d7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2389,8 +2389,8 @@ int intel_enable_rc6(const struct drm_device *dev)
> }
>
> /* snb/ivb have more than one rc6 state. */
> - if (INTEL_INFO(dev)->gen == 6) {
> - DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
> + if (INTEL_INFO(dev)->gen == 6 || IS_VALLEYVIEW(dev)) {
> + DRM_DEBUG_DRIVER("HW doesn't support deep RC6 (disabling)\n");
> return INTEL_RC6_ENABLE;
> }
>
> --
> 1.7.12
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2012-09-26 12:06 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-18 0:10 [PATCH] drm/i915: Valleyview doesn't have rc6+ or rc6++ Ben Widawsky
2012-09-18 21:01 ` Rodrigo Vivi
2012-09-26 12:06 ` Daniel Vetter [this message]
2012-09-27 15:34 ` Ben Widawsky
2012-09-27 16:32 ` Daniel Vetter
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