From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/i915: Document the multi-threaded FORCEWAKE bits
Date: Wed, 17 Oct 2012 09:27:24 -0700 [thread overview]
Message-ID: <20121017092724.22093e1c@jbarnes-desktop> (raw)
In-Reply-To: <1350472195-8051-2-git-send-email-chris@chris-wilson.co.uk>
On Wed, 17 Oct 2012 12:09:55 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:
> No functional change, but reserves 0x2 for use by userspace.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_pm.c | 10 +++++-----
> 2 files changed, 7 insertions(+), 5 deletions(-)
Each of the bits in this reg correspond to a specific agent that may
need to wake the GT. Unfortunately I don't have docs about which bits
are used by which agents. IIRC the BIOS uses one as does the AMT
engine if present.
I'll try to find out who owns each and maybe we can reserve our own for
userspace.
Thanks,
--
Jesse Barnes, Intel Open Source Technology Center
next prev parent reply other threads:[~2012-10-17 16:26 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-16 9:47 [PATCH] drm/i915: Set DERRMR around batches required vblank events Chris Wilson
2012-10-16 14:15 ` Daniel Vetter
2012-10-17 11:09 ` [PATCH 1/2] drm/i915: Allow DRM_ROOT_ONLY|DRM_MASTER to submit privileged batchbuffers Chris Wilson
2012-10-17 11:09 ` [PATCH 2/2] drm/i915: Document the multi-threaded FORCEWAKE bits Chris Wilson
2012-10-17 16:27 ` Jesse Barnes [this message]
2012-10-17 17:05 ` Jesse Barnes
2012-10-17 19:10 ` Daniel Vetter
2012-10-17 16:31 ` [PATCH 1/2] drm/i915: Allow DRM_ROOT_ONLY|DRM_MASTER to submit privileged batchbuffers Jesse Barnes
2012-10-17 19:09 ` Daniel Vetter
2012-10-17 18:47 ` Eric Anholt
2012-10-17 19:04 ` Daniel Vetter
2012-10-17 13:58 ` [PATCH] drm/i915: Set DERRMR around batches required vblank events Chris Wilson
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