From: Ben Widawsky <ben@bwidawsk.net>
To: ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+
Date: Tue, 19 Feb 2013 15:59:16 -0800 [thread overview]
Message-ID: <20130219235915.GA1701@bwidawsk.net> (raw)
In-Reply-To: <20130214224642.GA26753@bwidawsk.net>
On Thu, Feb 14, 2013 at 02:46:44PM -0800, Ben Widawsky wrote:
> On Thu, Feb 14, 2013 at 09:53:51PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The bit controlling whether PIPE_CONTROL DW/QW write targets
> > the global GTT or PPGTT moved moved from DW 2 bit 2 to
> > DW 1 bit 24 on IVB.
> >
> > I verified on IVB that the fix is in fact effective. Without the fix
> > none of the scratch writes actually landed in the pipe control page.
> > With the fix the writes show up correctly.
> >
> > v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
> [snip]
Reading the bspec again... do we want to set bit 21?
--
Ben Widawsky, Intel Open Source Technology Center
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next prev parent reply other threads:[~2013-02-19 23:57 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-14 19:53 [PATCH v2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+ ville.syrjala
2013-02-14 22:46 ` Ben Widawsky
2013-02-15 10:10 ` Daniel Vetter
2013-02-19 23:59 ` Ben Widawsky [this message]
2013-02-20 14:32 ` Ville Syrjälä
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