Re: [PATCH 11/11] drm/i915: limit DPFLIPSTAT enables to those we use on VLV

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Tue, Apr 02, 2013 at 11:09:30AM -0700, Jesse Barnes wrote:
> On Tue, 2 Apr 2013 13:37:50 +0300
> Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> 
> > On Thu, Mar 28, 2013 at 09:55:47AM -0700, Jesse Barnes wrote:
> > > Thus preventing the display from keeping the GT awake with unnecessary
> > > signals.
> > > 
> > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > > ---
> > >  drivers/gpu/drm/i915/intel_pm.c |    6 ++----
> > >  1 file changed, 2 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 2b02702..de9f898 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4116,11 +4116,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> > >  	 * when flip and other events complete.  So enable
> > >  	 * all the GUnit->GT interrupts here
> > >  	 */
> > > -	I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
> > > -		   PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
> > > +	I915_WRITE(VLV_DPFLIPSTAT,
> > >  		   SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
> > > -		   PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
> > > -		   PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
> > > +		   PLANEB_FLIPDONE_INT_EN |
> > >  		   SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
> > >  		   PLANEA_FLIPDONE_INT_EN);
> > 
> > We're not doing CS page flips w/ sprites currently, so I think you
> > could drop the sprite bits too.
> 
> Ok thanks, will drop.
> 
> > 
> > Actually, now that I think about it, do we need any bits enabled here?
> > i915_gem_execbuffer_wait_for_flips() is gone, so AFAICS GT no longer
> > needs to know when page flips complete.
> 
> We still use the flipdone interrupt for tracking fb state though, for
> unpinning the buffer.

AFAIK this register only controls the display->GT signals, but
shouldn't affect the CPU display interrupts.

-- 
Ville Syrjälä
Intel OTC