From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>,
Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [PATCH] drm/i915: Don't override PPGTT cacheability on HSW
Date: Thu, 4 Apr 2013 14:31:09 +0300 [thread overview]
Message-ID: <20130404113109.GZ4469@intel.com> (raw)
In-Reply-To: <CAKMK7uGMUR80bpfS_XxXoewOgE4oXFUex6ykq+xUukC=QfLnZA@mail.gmail.com>
On Wed, Apr 03, 2013 at 10:08:26PM +0200, Daniel Vetter wrote:
> On Wed, Apr 3, 2013 at 9:33 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
> > So I've checked hsw bspec and the problem is that hw guys again
> > changed the bits around a bit, and I think on HSW we actually want
> > (0x8 << 3) instead of what's currently there.
>
> Meh, I've screwed up reading the tables, 0x3 << 3 is what we imo want,
> so nothing needs to be changed. Sorry for the confusion.
Shouldn't it be (1<<3) on IVB (for just LLC w/o GFDT), and (3<<3) on
the rest?
Also what about the GAC_ECO_BITS register? BSpec tells me it exists on
IVB and HSW as well. It also seems to have a bit very similar to
ECOCHK_SNB_BIT but we don't actually set it on SNB.
--
Ville Syrjälä
Intel OTC
prev parent reply other threads:[~2013-04-04 11:31 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-03 18:06 [PATCH] drm/i915: Don't override PPGTT cacheability on HSW Ben Widawsky
2013-04-03 19:17 ` Kenneth Graunke
2013-04-03 19:33 ` Daniel Vetter
2013-04-03 20:08 ` Daniel Vetter
2013-04-03 20:41 ` Ben Widawsky
2013-04-03 23:30 ` Ben Widawsky
2013-04-04 11:31 ` Ville Syrjälä [this message]
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