From: Daniel Vetter <daniel@ffwll.ch>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH 1/2] drm/i915: report Gen5+ CPU and PCH FIFO underruns
Date: Fri, 19 Apr 2013 09:34:15 +0200 [thread overview]
Message-ID: <20130419073415.GO6169@phenom.ffwll.local> (raw)
In-Reply-To: <1366316957.3790.4.camel@ideak-mobl>
On Thu, Apr 18, 2013 at 11:29:17PM +0300, Imre Deak wrote:
> On Fri, 2013-04-12 at 17:57 -0300, Paulo Zanoni wrote:
> > +static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
> > + enum transcoder pch_transcoder,
> > + bool enable)
> > +{
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > + if (enable) {
> > + if (!cpt_can_enable_serr_int(dev))
> > + return;
> > +
> > + I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN |
> > + SERR_INT_TRANS_B_FIFO_UNDERRUN |
> > + SERR_INT_TRANS_C_FIFO_UNDERRUN);
>
> We end up here for LPT too, but there only the TRANS_A bit is defined.
We have the same issue on cpt where there's not really a pipe C on the
pch. I guess it doesn't really matter.
> Otherwise looks good:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
Queued for -next, thanks for the patch and review.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
prev parent reply other threads:[~2013-04-19 7:31 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-12 20:57 [PATCH 1/2] drm/i915: report Gen5+ CPU and PCH FIFO underruns Paulo Zanoni
2013-04-12 20:57 ` [PATCH 2/2] drm/i915: print Gen5+ CPU/PCH poison interrupts Paulo Zanoni
2013-04-18 20:47 ` Imre Deak
2013-04-19 7:34 ` Daniel Vetter
2013-04-18 20:29 ` [PATCH 1/2] drm/i915: report Gen5+ CPU and PCH FIFO underruns Imre Deak
2013-04-19 7:34 ` Daniel Vetter [this message]
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